From 62b29b0b758989879170660dd82cd32a0f94cd5d Mon Sep 17 00:00:00 2001 From: trayres Date: Wed, 14 May 2025 10:05:07 -0700 Subject: [PATCH] smt2 backend produces verilog testbench which errors out with Verilator; genclock is defined twice. This patch removes the redefinition of genclock. --- backends/smt2/smtbmc.py | 1 - 1 file changed, 1 deletion(-) diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py index d17bad3fb..31e814f90 100644 --- a/backends/smt2/smtbmc.py +++ b/backends/smt2/smtbmc.py @@ -1161,7 +1161,6 @@ def write_vlogtb_trace(steps, index): print(" initial genclock = 1;", file=f) print("`endif", file=f) - print(" reg genclock = 1;", file=f) print(" reg [31:0] cycle = 0;", file=f) primary_inputs = list()