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docs: restore and update the note about if/case attributes.
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@ -377,4 +377,7 @@ from SystemVerilog:
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- Assignments within expressions are supported.
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- The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are
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supported on ``if`` and ``case`` conditionals.
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supported on ``if`` and ``case`` conditionals. (The Verilog frontend
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will process conditionals using these keywords by annotating their
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representation with the appropriate ``full_case`` and/or ``parallel_case``
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attributes, which are described above.)
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