From 62660b221f7e106dd3d966775a49f96fe65e2248 Mon Sep 17 00:00:00 2001 From: Gary Wong Date: Fri, 30 May 2025 21:13:20 -0600 Subject: [PATCH] docs: restore and update the note about if/case attributes. --- docs/source/yosys_internals/verilog.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/yosys_internals/verilog.rst b/docs/source/yosys_internals/verilog.rst index 128280c06..0039aaab7 100644 --- a/docs/source/yosys_internals/verilog.rst +++ b/docs/source/yosys_internals/verilog.rst @@ -377,4 +377,7 @@ from SystemVerilog: - Assignments within expressions are supported. - The ``unique``, ``unique0``, and ``priority`` SystemVerilog keywords are - supported on ``if`` and ``case`` conditionals. + supported on ``if`` and ``case`` conditionals. (The Verilog frontend + will process conditionals using these keywords by annotating their + representation with the appropriate ``full_case`` and/or ``parallel_case`` + attributes, which are described above.)