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Add first draft of functional SB_MAC16 model

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-02-19 13:42:21 +01:00
parent 5a853ed46c
commit 62493c91b2
4 changed files with 467 additions and 53 deletions
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6
techlibs/ice40/tests/test_dsp_model.sh Normal file
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#!/bin/bash
set -ex
sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
./test_dsp_model