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Make testcase clearer with \o having its own init
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@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts
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design -reset
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design -reset
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read_verilog -icells <<EOT
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read_verilog -icells <<EOT
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module top(input clk, i, output o, p);
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module top(input clk, i, output o, p);
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(* init = 1'b0 *)
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wire o;
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(* init = 1'bx *)
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(* init = 1'bx *)
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wire p = o;
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wire p = o;
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$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
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$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
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