mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-11 03:33:36 +00:00
17 lines
262 B
Plaintext
17 lines
262 B
Plaintext
read_verilog -sv initval.v
|
|
proc;;
|
|
|
|
sat -seq 10 -prove-asserts
|
|
|
|
design -reset
|
|
read_verilog -icells <<EOT
|
|
module top(input clk, i, output o, p);
|
|
(* init = 1'b0 *)
|
|
wire o;
|
|
(* init = 1'bx *)
|
|
wire p = o;
|
|
$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
|
|
endmodule
|
|
EOT
|
|
sat -seq 1
|