mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-17 09:56:40 +00:00
Code Activity

Progress in examples/gowin/

Browse source
This commit is contained in:
Clifford Wolf 2016-11-08 19:07:22 +01:00
parent e9d73d2ee0
commit 617693e691
5 changed files with 95 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

9
examples/gowin/demo.v
View file

@ -1,11 +1,12 @@
module demo (
input clk,
output led1, led2, led3, led4, led5, led6, led7, led8,
output led9, led10, led11, led12, led13, led14, led15, led16
input [3:0] sw,
output [15:0] leds,
output [7:0] seg7dig,
output [3:0] seg7sel
);
localparam PRESCALE = 20;
reg [PRESCALE+3:0] counter = 0;
always @(posedge clk) counter <= counter + 1;
assign {led1, led2, led3, led4, led5, led6, led7, led8,
led9, led10, led11, led12, led13, led14, led15, led16} = 1 << counter[PRESCALE +: 4];
assign leds = 1 << counter[PRESCALE +: 4];
endmodule