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13 lines
273 B
Verilog
13 lines
273 B
Verilog
module demo (
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input clk,
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input [3:0] sw,
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output [15:0] leds,
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output [7:0] seg7dig,
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output [3:0] seg7sel
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);
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localparam PRESCALE = 20;
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reg [PRESCALE+3:0] counter = 0;
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always @(posedge clk) counter <= counter + 1;
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assign leds = 1 << counter[PRESCALE +: 4];
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endmodule
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