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verilog_parser: add port renaming tests

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xiota 2025-10-18 01:03:41 +00:00
parent 5b989b53f5
commit 60ae44dae8
7 changed files with 105 additions and 0 deletions
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14
tests/verilog/port_rename_pass_1.ys Normal file
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# Partial aliasing
read_verilog << EOF
module gate_swap (
.a(a),
.b(b),
c
);
input a;
input b;
output c;
assign c = a & !b;
endmodule
EOF
design -reset