mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-24 22:51:34 +00:00
14 lines
180 B
Text
14 lines
180 B
Text
# Partial aliasing
|
|
read_verilog << EOF
|
|
module gate_swap (
|
|
.a(a),
|
|
.b(b),
|
|
c
|
|
);
|
|
input a;
|
|
input b;
|
|
output c;
|
|
assign c = a & !b;
|
|
endmodule
|
|
EOF
|
|
design -reset
|