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verilog: add support for SystemVerilog string literals.

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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
This commit is contained in:
Gary Wong 2025-07-03 20:51:12 -06:00
parent 7b0c1fe491
commit 5feb1a1752
4 changed files with 386 additions and 47 deletions
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5
tests/verilog/bug5160.v
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@ -1,5 +0,0 @@
// Regression test for bug mentioned in #5160:
// https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
module top;
initial $display( "\\" );
endmodule