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Merge pull request #5361 from YosysHQ/emil/simplemap-transfer-src
simplemap: fix src attribute transfer
This commit is contained in:
Emil J
GitHub
commit
5f6819fd76
2 changed files with 30 additions and 18 deletions
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@ -18,6 +18,7 @@
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*/
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#include "simplemap.h"
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#include "backends/rtlil/rtlil_backend.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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#include <stdlib.h>
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@ -27,6 +28,14 @@
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USING_YOSYS_NAMESPACE
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YOSYS_NAMESPACE_BEGIN
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static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) {
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if (from->has_attribute(attr))
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to->attributes[attr] = from->attributes.at(attr);
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}
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static void transfer_src (Cell* to, const Cell* from) {
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transfer_attr(to, from, ID::src);
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}
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void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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@ -36,7 +45,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::Y, sig_y[i]);
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}
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@ -96,7 +105,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_b[i]);
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gate->setPort(ID::Y, sig_y[i]);
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@ -147,11 +156,14 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->attributes[ID::src] = cell->attributes[ID::src];
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log("huh\n");
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RTLIL_BACKEND::dump_cell(std::cout, "", cell);
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_a[i+1]);
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gate->setPort(ID::Y, sig_t[i/2]);
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last_output_cell = gate;
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RTLIL_BACKEND::dump_cell(std::cout, "", gate);
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}
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sig_a = sig_t;
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@ -160,7 +172,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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if (cell->type == ID($reduce_xnor)) {
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a);
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gate->setPort(ID::Y, sig_t);
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last_output_cell = gate;
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@ -188,7 +200,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig[i]);
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gate->setPort(ID::B, sig[i+1]);
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gate->setPort(ID::Y, sig_t[i/2]);
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@ -217,7 +229,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a);
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gate->setPort(ID::Y, sig_y);
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}
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@ -246,7 +258,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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log_assert(!gate_type.empty());
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a);
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gate->setPort(ID::B, sig_b);
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gate->setPort(ID::Y, sig_y);
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@ -262,19 +274,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
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RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
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RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
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xor_cell->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(xor_cell, cell);
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simplemap_bitop(module, xor_cell);
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module->remove(xor_cell);
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RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
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RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
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reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(reduce_cell, cell);
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simplemap_reduce(module, reduce_cell);
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module->remove(reduce_cell);
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if (!is_ne) {
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RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
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not_cell->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(not_cell, cell);
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simplemap_lognot(module, not_cell);
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module->remove(not_cell);
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}
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@ -288,7 +300,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_b[i]);
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gate->setPort(ID::S, cell->getPort(ID::S));
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@ -305,7 +317,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_b[i]);
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gate->setPort(ID::S, sig_s[i]);
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@ -321,7 +333,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::E, sig_e);
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gate->setPort(ID::Y, sig_y[i]);
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@ -339,7 +351,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
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for (int i = 0; i < GetSize(new_data); i += width) {
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for (int k = 0; k < width; k++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, data[i*2+k]);
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gate->setPort(ID::B, data[i*2+width+k]);
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gate->setPort(ID::S, sel[idx]);
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@ -362,7 +374,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
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SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
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for (int i = 0; i < GetSize(lut_data); i += 2) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
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gate->attributes[ID::src] = cell->attributes[ID::src];
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transfer_src(gate, cell);
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gate->setPort(ID::A, lut_data[i]);
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gate->setPort(ID::B, lut_data[i+1]);
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gate->setPort(ID::S, lut_ctrl[idx]);
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@ -32,8 +32,8 @@ proc
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equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd mux8 # Constrain all select calls below inside the top module
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select -assert-count 1 t:LUT1
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select -assert-count 10 t:LUT3
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select -assert-count 3 t:LUT1
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select -assert-count 2 t:LUT3
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select -assert-count 1 t:LUT4
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select -assert-count 5 t:MUX2_LUT5
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select -assert-count 2 t:MUX2_LUT6
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