From 96f87aa2d43aab7c21293cbc32c2699ca0a36276 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Thu, 18 Sep 2025 12:59:12 +0200 Subject: [PATCH 1/2] simplemap: fix src attribute transfer --- passes/techmap/simplemap.cc | 44 +++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index ddfd7e03e..86ff5c149 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -18,6 +18,7 @@ */ #include "simplemap.h" +#include "backends/rtlil/rtlil_backend.h" #include "kernel/sigtools.h" #include "kernel/ff.h" #include @@ -27,6 +28,14 @@ USING_YOSYS_NAMESPACE YOSYS_NAMESPACE_BEGIN +static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) { + if (from->has_attribute(attr)) + to->attributes[attr] = from->attributes.at(attr); +} +static void transfer_src (Cell* to, const Cell* from) { + transfer_attr(to, from, ID::src); +} + void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) { RTLIL::SigSpec sig_a = cell->getPort(ID::A); @@ -36,7 +45,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -96,7 +105,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::Y, sig_y[i]); @@ -147,11 +156,14 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + log("huh\n"); + RTLIL_BACKEND::dump_cell(std::cout, "", cell); + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); gate->setPort(ID::Y, sig_t[i/2]); last_output_cell = gate; + RTLIL_BACKEND::dump_cell(std::cout, "", gate); } sig_a = sig_t; @@ -160,7 +172,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($reduce_xnor)) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); last_output_cell = gate; @@ -188,7 +200,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -217,7 +229,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); } @@ -246,7 +258,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); gate->setPort(ID::Y, sig_y); @@ -262,20 +274,20 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); - xor_cell->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(xor_cell, cell); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); - reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(reduce_cell, cell); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); - not_cell->attributes[ID::src] = cell->attributes[ID::src]; - simplemap_lognot(module, not_cell); + transfer_src(not_cell, cell); + simplemap_lognot(module, not_cell); module->remove(not_cell); } } @@ -288,7 +300,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, cell->getPort(ID::S)); @@ -305,7 +317,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, sig_s[i]); @@ -321,7 +333,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); gate->setPort(ID::Y, sig_y[i]); @@ -339,7 +351,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, data[i*2+k]); gate->setPort(ID::B, data[i*2+width+k]); gate->setPort(ID::S, sel[idx]); @@ -362,7 +374,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + transfer_src(gate, cell); gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); gate->setPort(ID::S, lut_ctrl[idx]); From 6527cc2134c818b0084a47c82e664c8d198725dc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Emil=20Ji=C5=99=C3=AD=20Tywoniak?= Date: Tue, 23 Sep 2025 20:03:50 +0200 Subject: [PATCH 2/2] gowin: fix test --- tests/arch/gowin/mux.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index d5978f4ea..2ca973520 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -32,8 +32,8 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT1 -select -assert-count 10 t:LUT3 +select -assert-count 3 t:LUT1 +select -assert-count 2 t:LUT3 select -assert-count 1 t:LUT4 select -assert-count 5 t:MUX2_LUT5 select -assert-count 2 t:MUX2_LUT6