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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit 5e72464a15
5 changed files with 31 additions and 0 deletions
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3
backends/verilog/verilog_backend.cc
View file

@ -419,6 +419,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset); range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset);
else else
range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset); range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset);
} else {
if (wire->attributes.count(ID::single_bit_vector))
range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
} }
if (wire->port_input && !wire->port_output) if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());

1
frontends/ast/genrtlil.cc
View file

@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input; wire->port_input = is_input;
wire->port_output = is_output; wire->port_output = is_output;
wire->upto = range_swapped; wire->upto = range_swapped;
wire->is_signed = is_signed; wire->is_signed = is_signed;
for (auto &attr : attributes) { for (auto &attr : attributes) {

6
frontends/ast/simplify.cc
View file

@ -2084,6 +2084,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
std::swap(range_left, range_right); std::swap(range_left, range_right);
range_swapped = force_upto; range_swapped = force_upto;
} }
if (range_left == range_right)
set_attribute(ID::single_bit_vector, mkconst_int(1, false));
} }
} else { } else {
if (!range_valid) if (!range_valid)
@ -2092,6 +2094,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
range_swapped = false; range_swapped = false;
range_left = 0; range_left = 0;
range_right = 0; range_right = 0;
if (attributes.count(ID::single_bit_vector)) {
delete attributes[ID::single_bit_vector];
attributes.erase(ID::single_bit_vector);
}
} }
} }

1
kernel/constids.inc
View file

@ -184,6 +184,7 @@ X(romstyle)
X(S) X(S)
X(SET) X(SET)
X(SET_POLARITY) X(SET_POLARITY)
X(single_bit_vector)
X(SIZE) X(SIZE)
X(SRC) X(SRC)
X(src) X(src)

20
tests/verilog/sbvector.ys Normal file
View file

@ -0,0 +1,20 @@
read_verilog <<EOT
module foo(
output o,
input [0:0] i1,
input i2
);
assign o = i1 ^ i2;
endmodule
EOT
logger -expect log "wire width 1 input 2 \\i1" 1
logger -expect log "wire input 3 \\i2" 1
dump
logger -check-expected
write_verilog verilog_sbvector.out
!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
!grep -qF 'input [0:0] i1;' verilog_sbvector.out
!grep -qF 'wire i2;' verilog_sbvector.out
!grep -qF 'input i2;' verilog_sbvector.out