diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 2bc6ff3b8..1b828dcbd 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -419,6 +419,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 			range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset);
 		else
 			range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset);
+	} else {
+		if (wire->attributes.count(ID::single_bit_vector))
+			range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
 	}
 	if (wire->port_input && !wire->port_output)
 		f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d3982b92b..26ed0e3e4 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			wire->port_input = is_input;
 			wire->port_output = is_output;
 			wire->upto = range_swapped;
+
 			wire->is_signed = is_signed;
 
 			for (auto &attr : attributes) {
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 3411d6c03..a45eb1cc1 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2084,6 +2084,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 					std::swap(range_left, range_right);
 					range_swapped = force_upto;
 				}
+				if (range_left == range_right)
+					set_attribute(ID::single_bit_vector, mkconst_int(1, false));
 			}
 		} else {
 			if (!range_valid)
@@ -2092,6 +2094,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 			range_swapped = false;
 			range_left = 0;
 			range_right = 0;
+			if (attributes.count(ID::single_bit_vector)) {
+				delete attributes[ID::single_bit_vector];
+				attributes.erase(ID::single_bit_vector);
+			}
 		}
 	}
 
diff --git a/kernel/constids.inc b/kernel/constids.inc
index 4fdbb3dc8..055ebf2a8 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -184,6 +184,7 @@ X(romstyle)
 X(S)
 X(SET)
 X(SET_POLARITY)
+X(single_bit_vector)
 X(SIZE)
 X(SRC)
 X(src)
diff --git a/tests/verilog/sbvector.ys b/tests/verilog/sbvector.ys
new file mode 100644
index 000000000..3481f6f45
--- /dev/null
+++ b/tests/verilog/sbvector.ys
@@ -0,0 +1,20 @@
+read_verilog <<EOT
+module foo(
+	output o,
+	input [0:0] i1,
+	input i2
+);
+	assign o = i1 ^ i2;
+endmodule
+EOT
+
+logger -expect log "wire width 1 input 2 \\i1" 1
+logger -expect log "wire input 3 \\i2" 1
+dump
+logger -check-expected
+
+write_verilog verilog_sbvector.out
+!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
+!grep -qF 'input [0:0] i1;' verilog_sbvector.out
+!grep -qF 'wire i2;' verilog_sbvector.out
+!grep -qF 'input i2;' verilog_sbvector.out