mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-14 11:14:44 +00:00
Code Activity

rtlil: enable single-bit vector wires

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit 5e72464a15
5 changed files with 31 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
frontends/ast/simplify.cc
View file

@ -2084,6 +2084,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
std::swap(range_left, range_right);
range_swapped = force_upto;
}
if (range_left == range_right)
set_attribute(ID::single_bit_vector, mkconst_int(1, false));
}
} else {
if (!range_valid)
@ -2092,6 +2094,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
range_swapped = false;
range_left = 0;
range_right = 0;
if (attributes.count(ID::single_bit_vector)) {
delete attributes[ID::single_bit_vector];
attributes.erase(ID::single_bit_vector);
}
}
}