mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-17 12:44:46 +00:00
Code Activity

rtlil: enable single-bit vector wires

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit 5e72464a15
5 changed files with 31 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/ast/genrtlil.cc
View file

@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
wire->is_signed = is_signed;
for (auto &attr : attributes) {