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José Miguel Sánchez García 2025-03-29 20:35:42 +01:00 committed by GitHub
commit 5e07924e32
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@ -1395,7 +1395,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
if (child->type == AST_MODULE || child->type == AST_INTERFACE)
{
for (auto n : design->verilog_globals)
child->children.push_back(n->clone());
child->children.insert(child->children.begin(), n->clone());
// append nodes from previous packages using package-qualified names
for (auto &n : design->verilog_packages) {