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signorm: an unconnected output port does not claim a driver
setup_driven_wires() gave a zero-width port connection -- an output left unattached, `.q_bar()` -- a helper wire and recorded the cell as its driver. Nothing ever retracts that: unsetPort skips zero-width connections, as does signorm_index_add when adding them. So removing the cell left the helper wire pointing at freed memory, and the next `check` dereferenced it. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
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@ -118,6 +118,14 @@ struct RTLIL::SigNormIndex
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xlog("\t%s = %s\n", module->design->twines.str(port).c_str(), log_signal(sig));
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if (cell->port_dir(port) == RTLIL::PD_INPUT)
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continue;
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// An output left unconnected (`.q_bar()`) drives nothing, and
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// `signorm_index_add` declines to record a zero-width one.
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// Claiming a driver here anyway leaves a wire pointing at the
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// cell that `unsetPort` will never clear, because it too skips
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// zero-width connections -- so removing the cell strands the
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// wire on freed memory.
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if (GetSize(sig) == 0)
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continue;
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xlog("%s is not an input in design %p\n", module->design->twines.str(port).c_str(), module->design);
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if (sig.is_wire()) {
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Wire * wire = sig.as_wire();
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