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rtlil: register a cloned cell's ports with the signorm index

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addCell(name, other) assigned connections_ wholesale, so a clone made while
the module carries an index was invisible to it: its inputs were absent from
the fanout and its outputs claimed no driver. The first setPort on the clone
then tried to retract entries that had never been made and tripped the
`erased' assertion. Go through setPort instead, which also interposes a wire
wherever the original is still driving the net.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
This commit is contained in:
Emil J. Tywoniak 2026-07-21 19:20:42 +02:00
parent 1b9b594f52
commit 7adb81e36e
1 changed files with 14 additions and 6 deletions
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20
kernel/rtlil.cc
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@ -3824,14 +3824,22 @@ RTLIL::Cell *RTLIL::Module::addCell(TwineRef name, const RTLIL::Cell *other)
type = this->design->twines.copy_from(src_design->twines, other->type_impl);
RTLIL::Cell *cell = addCell(name, type);
if (cross_pool) {
for (auto &c : other->connections_)
cell->connections_[this->design->twines.copy_from(src_design->twines, c.first)] = c.second;
} else {
cell->connections_ = other->connections_;
}
cell->parameters = other->parameters;
cell->attributes = other->attributes;
// Storing the connections directly would leave a signorm index blind to
// the clone: its inputs would be absent from the fanout and its outputs
// would claim no driver, so the first setPort on the clone would try to
// retract entries that were never made. Go through setPort there, which
// also interposes a wire wherever the original is still driving the net.
bool indexed = signorm_indexed();
for (auto &c : other->connections_) {
TwineRef port = cross_pool ? this->design->twines.copy_from(src_design->twines, c.first) : c.first;
if (indexed)
cell->setPort(port, c.second);
else
cell->connections_[port] = c.second;
}
if (src_design && this->design)
copy_src_into(other, src_design, cell, this->design);
return cell;