From 5cd9efefe3eb4af179f326515a9891badf34fd91 Mon Sep 17 00:00:00 2001
From: Michael Baier <mb+git@katzfink.at>
Date: Thu, 9 Jul 2026 10:41:42 +0200
Subject: [PATCH] Adding widht checks to backend

---
 kernel/rtlil.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d7503d5e2..89cd1b244 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -379,6 +379,7 @@ RTLIL::Const::Const(long long val) // default width 32
 
 RTLIL::Const::Const(long long val, int width)
 {
+	log_assert(width >= 0 && width < RTLIL::WIDTH_LIMIT);
 	flags = RTLIL::CONST_FLAG_NONE;
 	if ((width & 7) == 0) {
 		new ((void*)&str_) std::string();
@@ -407,6 +408,7 @@ RTLIL::Const::Const(long long val, int width)
 
 RTLIL::Const::Const(RTLIL::State bit, int width)
 {
+	log_assert(width >= 0 && width < RTLIL::WIDTH_LIMIT);
 	flags = RTLIL::CONST_FLAG_NONE;
 	new ((void*)&bits_) bitvectype();
 	tag = backing_tag::bits;
@@ -3170,6 +3172,7 @@ void RTLIL::Module::fixup_ports()
 
 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)
 {
+	log_assert(width >= 0 && width < RTLIL::WIDTH_LIMIT);
 	RTLIL::Wire *wire = new RTLIL::Wire;
 	wire->name = std::move(name);
 	wire->width = width;