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Sync with upstream

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This commit is contained in:
Akash Levy 2025-01-13 17:20:59 -08:00
commit 5c514e00a4
15 changed files with 183 additions and 79 deletions
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2
passes/techmap/alumacc.cc
View file

@ -283,7 +283,7 @@ struct AlumaccWorker
for (auto &it : sig_macc)
{
auto n = it.second;
RTLIL::SigSpec A, B, C = n->macc.bit_ports;
RTLIL::SigSpec A, B, C;
bool a_signed = false, b_signed = false;
bool subtract_b = false;
alunode_t *alunode;

42
passes/techmap/flatten.cc
View file

@ -28,19 +28,25 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
IdString concat_name(RTLIL::Cell *cell, IdString object_name)
IdString concat_name(RTLIL::Cell *cell, IdString object_name, const std::string &separator = ".")
{
if (object_name[0] == '\\')
return stringf("%s.%s", cell->name.c_str(), object_name.c_str() + 1);
return stringf("%s%s%s", cell->name.c_str(), separator.c_str(), object_name.c_str() + 1);
else {
return stringf("%s.%s", cell->name.c_str(), object_name.c_str());
/*
std::string object_name_str = object_name.str();
if (object_name_str.substr(0, 8) == "$flatten")
object_name_str.erase(0, 8);
return stringf("$flatten%s%s%s", cell->name.c_str(), separator.c_str(), object_name_str.c_str());
*/
}
}
template<class T>
IdString map_name(RTLIL::Cell *cell, T *object)
IdString map_name(RTLIL::Cell *cell, T *object, const std::string &separator = ".")
{
return cell->module->uniquify(concat_name(cell, object->name));
return cell->module->uniquify(concat_name(cell, object->name, separator));
}
void map_sigspec(const dict<RTLIL::Wire*, RTLIL::Wire*> &map, RTLIL::SigSpec &sig, RTLIL::Module *into = nullptr)
@ -57,6 +63,7 @@ struct FlattenWorker
bool ignore_wb = false;
bool create_scopeinfo = false; // SILIMATE: default false
bool create_scopename = false;
std::string separator = ".";
template<class T>
void map_attributes(RTLIL::Cell *cell, T *object, IdString orig_object_name)
@ -104,13 +111,13 @@ struct FlattenWorker
}
}
void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, SigMap &sigmap, std::vector<RTLIL::Cell*> &new_cells)
void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, SigMap &sigmap, std::vector<RTLIL::Cell*> &new_cells, const std::string &separator)
{
// Copy the contents of the flattened cell
dict<IdString, IdString> memory_map;
for (auto &tpl_memory_it : tpl->memories) {
RTLIL::Memory *new_memory = module->addMemory(map_name(cell, tpl_memory_it.second), tpl_memory_it.second);
RTLIL::Memory *new_memory = module->addMemory(map_name(cell, tpl_memory_it.second, separator), tpl_memory_it.second);
map_attributes(cell, new_memory, tpl_memory_it.second->name);
memory_map[tpl_memory_it.first] = new_memory->name;
design->select(module, new_memory);
@ -124,7 +131,7 @@ struct FlattenWorker
RTLIL::Wire *new_wire = nullptr;
if (tpl_wire->name[0] == '\\') {
RTLIL::Wire *hier_wire = module->wire(concat_name(cell, tpl_wire->name));
RTLIL::Wire *hier_wire = module->wire(concat_name(cell, tpl_wire->name, separator));
if (hier_wire != nullptr && hier_wire->get_bool_attribute(ID::hierconn)) {
hier_wire->attributes.erase(ID::hierconn);
if (GetSize(hier_wire) < GetSize(tpl_wire)) {
@ -136,7 +143,7 @@ struct FlattenWorker
}
}
if (new_wire == nullptr) {
new_wire = module->addWire(map_name(cell, tpl_wire), tpl_wire);
new_wire = module->addWire(map_name(cell, tpl_wire, separator), tpl_wire);
new_wire->port_input = new_wire->port_output = false;
new_wire->port_id = false;
}
@ -147,7 +154,7 @@ struct FlattenWorker
}
for (auto &tpl_proc_it : tpl->processes) {
RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second);
RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second, separator), tpl_proc_it.second);
map_attributes(cell, new_proc, tpl_proc_it.second->name);
for (auto new_proc_sync : new_proc->syncs)
for (auto &memwr_action : new_proc_sync->mem_write_actions)
@ -158,14 +165,14 @@ struct FlattenWorker
}
for (auto tpl_cell : tpl->cells()) {
RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell), tpl_cell);
RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell, separator), tpl_cell);
map_attributes(cell, new_cell, tpl_cell->name);
if (new_cell->has_memid()) {
IdString memid = new_cell->getParam(ID::MEMID).decode_string();
new_cell->setParam(ID::MEMID, Const(memory_map.at(memid).str()));
} else if (new_cell->is_mem_cell()) {
IdString memid = new_cell->getParam(ID::MEMID).decode_string();
new_cell->setParam(ID::MEMID, Const(concat_name(cell, memid).str()));
new_cell->setParam(ID::MEMID, Const(concat_name(cell, memid, separator).str()));
}
auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
new_cell->rewrite_sigspecs(rewriter);
@ -276,7 +283,7 @@ struct FlattenWorker
module->rename(scopeinfo, cell_name);
}
void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Module*> &used_modules)
void flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Module*> &used_modules, const std::string &separator)
{
if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
return;
@ -305,7 +312,7 @@ struct FlattenWorker
// If a design is fully selected and has a top module defined, topological sorting ensures that all cells
// added during flattening are black boxes, and flattening is finished in one pass. However, when flattening
// individual modules, this isn't the case, and the newly added cells might have to be flattened further.
flatten_cell(design, module, cell, tpl, sigmap, worklist);
flatten_cell(design, module, cell, tpl, sigmap, worklist, separator);
}
}
};
@ -342,6 +349,9 @@ struct FlattenPass : public Pass {
log(" with a public name the enclosing scope can be found via their\n");
log(" 'hdlname' attribute.\n");
log("\n");
log(" -separator <char>\n");
log(" Use this separator char instead of '.' when concatenating design levels.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
@ -364,6 +374,10 @@ struct FlattenPass : public Pass {
worker.create_scopename = true;
continue;
}
if (args[argidx] == "-separator" && argidx + 1 < args.size()) {
worker.separator = args[++argidx];
continue;
}
break;
}
extra_args(args, argidx, design);
@ -398,7 +412,7 @@ struct FlattenPass : public Pass {
log_error("Cannot flatten a design containing recursive instantiations.\n");
for (auto module : topo_modules.sorted)
worker.flatten_module(design, module, used_modules);
worker.flatten_module(design, module, used_modules, worker.separator);
if (top != nullptr)
for (auto module : design->modules().to_vector())

24
passes/techmap/maccmap.cc
View file

@ -286,19 +286,23 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b),
GetSize(port.in_a), GetSize(port.in_b), port.is_signed ? "signed" : "unsigned");
if (GetSize(macc.bit_ports) != 0)
log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), GetSize(macc.bit_ports));
if (unmap)
{
typedef std::pair<RTLIL::SigSpec, bool> summand_t;
std::vector<summand_t> summands;
RTLIL::SigSpec bit_ports;
for (auto &port : macc.ports) {
summand_t this_summand;
if (GetSize(port.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed);
} else if (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {
// Mimic old 'bit_ports' treatment in case it's relevant for performance,
// i.e. defer single-bit summands to be the last ones
bit_ports.append(port.in_a);
continue;
} else if (GetSize(port.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed);
@ -309,7 +313,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
summands.push_back(this_summand);
}
for (auto &bit : macc.bit_ports)
for (auto &bit : bit_ports)
summands.push_back(summand_t(bit, false));
if (GetSize(summands) == 0)
@ -346,14 +350,20 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
else
{
MaccmapWorker worker(module, width);
RTLIL::SigSpec bit_ports;
for (auto &port : macc.ports)
if (GetSize(port.in_b) == 0)
for (auto &port : macc.ports) {
// Mimic old 'bit_ports' treatment in case it's relevant for performance,
// i.e. defer single-bit summands to be the last ones
if (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract)
bit_ports.append(port.in_a);
else if (GetSize(port.in_b) == 0)
worker.add(port.in_a, port.is_signed, port.do_subtract);
else
worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract);
}
for (auto &bit : macc.bit_ports)
for (auto bit : bit_ports)
worker.add(bit, 0);
module->connect(cell->getPort(ID::Y), worker.synth());