mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Add test for bug 3462

Browse source
This commit is contained in:
Miodrag Milanovic 2022-08-29 10:10:09 +02:00
parent 4bc1e1d1f1
commit 5b5fe76966
2 changed files with 15 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

12
tests/various/bug3462.ys Normal file
View file

@ -0,0 +1,12 @@
read_verilog <<EOT
module top();
wire array[0:0];
wire out;
sub #(.d(1)) inst(
.in(array[0]),
.out(out)
);
endmodule
EOT
hierarchy -top top -libdir .

3
tests/various/sub.v Normal file
View file

@ -0,0 +1,3 @@
module sub #(parameter d=1) (input in, output out);
assign out = in;
endmodule