From 5b5fe76966b44ebc35e0087072c1df2c2bba044b Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 29 Aug 2022 10:10:09 +0200
Subject: [PATCH] Add test for bug 3462

---
 tests/various/bug3462.ys | 12 ++++++++++++
 tests/various/sub.v      |  3 +++
 2 files changed, 15 insertions(+)
 create mode 100644 tests/various/bug3462.ys
 create mode 100644 tests/various/sub.v

diff --git a/tests/various/bug3462.ys b/tests/various/bug3462.ys
new file mode 100644
index 000000000..c85dc9470
--- /dev/null
+++ b/tests/various/bug3462.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module top();
+    wire array[0:0];
+    wire out;
+    sub #(.d(1)) inst(
+        .in(array[0]),
+        .out(out)
+    );
+endmodule
+EOT
+
+hierarchy -top top -libdir .
diff --git a/tests/various/sub.v b/tests/various/sub.v
new file mode 100644
index 000000000..63422ca5c
--- /dev/null
+++ b/tests/various/sub.v
@@ -0,0 +1,3 @@
+module sub #(parameter d=1) (input in, output out);
+    assign out = in;
+endmodule