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rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design

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This commit is contained in:
Emil J. Tywoniak 2026-05-23 01:09:26 +02:00
parent b0eb50be1b
commit 5a6568edbe
3 changed files with 164 additions and 110 deletions
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9
kernel/unstable/patch.cc
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@ -118,24 +118,17 @@ void Patch::patch(Cell* old_cell, Cell* new_cell) {
auto dir = raw->port_dir(port_name);
log_assert(dir != PD_UNKNOWN);
if (dir == PD_OUTPUT || dir == PD_INOUT) {
SigSpec sig_to_fix = sig;
if (raw == new_cell) {
// RAUW
// TODO optimized implementation for signorm fanout transfer that avoids expensive(?) setPort?
auto yoink = old_cell->getPort(port_name);
log(">>>> RAUW %s to %s\n", port_name, log_signal(yoink));
new_cell->setPort(port_name, yoink);
old_cell->setPort(port_name, mod->addWire(NEW_ID, yoink.size()));
sig_to_fix = yoink;
}
if (sig_to_fix.size()) {
auto* wire = sig_to_fix.as_wire();
wire->driverCell_ = raw;
wire->driverPort_ = port_name;
}
}
}
raw->module = mod;
raw->initIndex();
raw->fixup_parameters();
}
log_module(mod, "");