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https://github.com/YosysHQ/yosys
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rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design
This commit is contained in:
Emil J. Tywoniak
parent
b0eb50be1b
commit
5a6568edbe
3 changed files with 164 additions and 110 deletions
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@ -1087,15 +1087,161 @@ static bool ignored_cell(const RTLIL::IdString& type)
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return type == ID($specify2) || type == ID($specify3) || type == ID($specrule);
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}
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void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_signal, bool is_input)
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{
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auto &index = *module->sig_norm_index;
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index.dirty.insert(this);
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if (is_input) {
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int i = 0;
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for (auto bit : old_signal) {
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if (bit.is_wire()) {
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auto found = index.fanout.find(bit);
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log_assert(found != index.fanout.end());
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int erased = found->second.erase(PortBit(this, portname, i));
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log_assert(erased);
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if (found->second.empty())
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index.fanout.erase(found);
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}
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i++;
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}
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} else {
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Wire *w = old_signal.as_wire();
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log_assert(w->driverCell_ == this);
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log_assert(w->driverPort_ == portname);
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w->driverCell_ = nullptr;
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w->driverPort_ = IdString();
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}
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}
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void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal, bool is_input)
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{
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auto &index = *module->sig_norm_index;
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index.dirty.insert(this);
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if (is_input) {
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int i = 0;
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for (auto bit : new_signal) {
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if (bit.is_wire())
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index.fanout[bit].insert(PortBit(this, portname, i));
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i++;
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}
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} else if (GetSize(new_signal)) {
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Wire *w = new_signal.as_wire();
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log_assert(w->driverCell_ == nullptr);
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log_assert(w->driverPort_.empty());
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w->driverCell_ = this;
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w->driverPort_ = portname;
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}
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}
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// Handles the bufnorm part of setPort. Updates conn_it->second and returns true if the
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// connection was stored (fast path or $connect cell). If false, caller must store signal.
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bool RTLIL::Cell::bufnorm_handle_setPort(IdString portname, SigSpec &signal, dict<IdString, SigSpec>::iterator conn_it)
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{
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// Eagerly clear a driver that got disconnected by changing this port connection
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if (conn_it->second.is_wire()) {
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Wire *w = conn_it->second.as_wire();
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if (w->driverCell_ == this && w->driverPort_ == portname) {
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w->driverCell_ = nullptr;
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w->driverPort_ = IdString();
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module->buf_norm_wire_queue.insert(w);
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}
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}
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auto dir = port_dir(portname);
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// Fast path: connecting a full driverless wire to an output port — everything else
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// goes through the bufnorm queues and is handled during the next bufNormalize call
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if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) {
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Wire *w = signal.as_wire();
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if (w->driverCell_ == nullptr &&
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(w->port_input && !w->port_output) == (type == ID($input_port))) {
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w->driverCell_ = this;
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w->driverPort_ = portname;
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conn_it->second = std::move(signal);
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return true;
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}
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}
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if (dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) {
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module->buf_norm_cell_queue.insert(this);
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module->buf_norm_cell_port_queue.emplace(this, portname);
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} else {
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for (auto &chunk : signal.chunks())
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if (chunk.wire != nullptr && chunk.wire->driverCell_ == nullptr)
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module->buf_norm_wire_queue.insert(chunk.wire);
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}
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if (type == ID($connect)) {
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for (auto &[port, sig] : connections_) {
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for (auto &chunk : sig.chunks()) {
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if (!chunk.wire) continue;
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auto it = module->buf_norm_connect_index.find(chunk.wire);
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if (it == module->buf_norm_connect_index.end()) continue;
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it->second.erase(this);
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if (it->second.empty())
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module->buf_norm_connect_index.erase(it);
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}
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}
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conn_it->second = std::move(signal);
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for (auto &[port, sig] : connections_) {
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for (auto &chunk : sig.chunks()) {
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if (!chunk.wire) continue;
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module->buf_norm_connect_index[chunk.wire].insert(this);
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}
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}
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return true;
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}
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return false;
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}
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// Called after the cell's module pointer has been set to push all existing port connections
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// into the signorm and bufnorm indices. Assumes signals are already in normalized form.
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void RTLIL::Cell::initIndex()
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{
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log_assert(module != nullptr);
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if (ignored_cell(type))
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return;
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if (module->sig_norm_index != nullptr) {
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for (auto &[portname, signal] : connections_) {
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bool is_input = port_dir(portname) == RTLIL::PD_INPUT;
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signorm_index_add(portname, signal, is_input);
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}
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}
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if (module->design && module->design->flagBufferedNormalized) {
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for (auto &[portname, signal] : connections_) {
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auto dir = port_dir(portname);
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if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) {
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Wire *w = signal.as_wire();
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if (w->driverCell_ == nullptr &&
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(w->port_input && !w->port_output) == (type == ID($input_port))) {
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w->driverCell_ = this;
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w->driverPort_ = portname;
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continue;
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}
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}
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if (dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) {
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module->buf_norm_cell_queue.insert(this);
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module->buf_norm_cell_port_queue.emplace(this, portname);
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} else {
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for (auto &chunk : signal.chunks())
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if (chunk.wire != nullptr && chunk.wire->driverCell_ == nullptr)
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module->buf_norm_wire_queue.insert(chunk.wire);
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}
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}
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}
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}
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void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
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{
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bool is_input_port = false;
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bool is_input = false;
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if (module && module->sig_norm_index != nullptr && !ignored_cell(type)) {
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module->sig_norm_index->sigmap.apply(signal);
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auto dir = port_dir(portname);
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if (dir == RTLIL::PD_INPUT) {
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is_input_port = true;
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is_input = true;
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} else {
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Wire *wire = nullptr;
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if (signal.is_wire() && (wire = signal.as_wire())->driverCell_ != nullptr)
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@ -1128,111 +1274,17 @@ void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
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}
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if (module && module->sig_norm_index != nullptr && !ignored_cell(type)) {
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module->sig_norm_index->dirty.insert(this);
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if (!r.second) {
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if (is_input_port) {
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auto &fanout = module->sig_norm_index->fanout;
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int i = 0;
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for (auto bit : conn_it->second) {
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if (bit.is_wire()) {
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auto found = fanout.find(bit);
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log_assert(found != fanout.end());
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int erased = found->second.erase(PortBit(this, portname, i));
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log_assert(erased);
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if (found->second.empty())
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fanout.erase(found);
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}
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i++;
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}
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} else {
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Wire *w = conn_it->second.as_wire();
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log_assert(w->driverCell_ == this);
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log_assert(w->driverPort_ == portname);
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w->driverCell_ = nullptr;
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w->driverPort_ = IdString();
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}
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}
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if (is_input_port) {
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auto &fanout = module->sig_norm_index->fanout;
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int i = 0;
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for (auto bit : signal) {
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if (bit.is_wire())
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fanout[bit].insert(PortBit(this, portname, i));
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i++;
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}
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} else if (GetSize(signal)) {
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Wire *w = signal.as_wire();
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log_assert(w->driverCell_ == nullptr);
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log_assert(w->driverPort_.empty());
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w->driverCell_ = this;
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w->driverPort_ = portname;
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}
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if (!r.second)
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signorm_index_remove(portname, conn_it->second, is_input);
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signorm_index_add(portname, signal, is_input);
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}
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if (module && module->design && module->design->flagBufferedNormalized)
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{
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// We eagerly clear a driver that got disconnected by changing this port connection
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if (conn_it->second.is_wire()) {
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Wire *w = conn_it->second.as_wire();
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if (w->driverCell_ == this && w->driverPort_ == portname) {
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w->driverCell_ = nullptr;
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w->driverPort_ = IdString();
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module->buf_norm_wire_queue.insert(w);
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}
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}
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auto dir = port_dir(portname);
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// This is a fast path that handles connecting a full driverless wire to an output port,
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// everything else is goes through the bufnorm queues and is handled during the next
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// bufNormalize call
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if ((dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) && signal.is_wire()) {
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Wire *w = signal.as_wire();
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if (w->driverCell_ == nullptr && (
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(w->port_input && !w->port_output) == (type == ID($input_port)))) {
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w->driverCell_ = this;
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w->driverPort_ = portname;
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conn_it->second = std::move(signal);
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return;
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}
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}
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if (dir == RTLIL::PD_OUTPUT || dir == RTLIL::PD_INOUT) {
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module->buf_norm_cell_queue.insert(this);
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module->buf_norm_cell_port_queue.emplace(this, portname);
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} else {
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for (auto &chunk : signal.chunks())
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if (chunk.wire != nullptr && chunk.wire->driverCell_ == nullptr)
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module->buf_norm_wire_queue.insert(chunk.wire);
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}
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if (type == ID($connect)) {
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for (auto &[port, sig] : connections_) {
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for (auto &chunk : sig.chunks()) {
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if (!chunk.wire)
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continue;
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auto it = module->buf_norm_connect_index.find(chunk.wire);
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if (it == module->buf_norm_connect_index.end())
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continue;
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it->second.erase(this);
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if (it->second.empty())
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module->buf_norm_connect_index.erase(it);
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}
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}
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conn_it->second = std::move(signal);
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for (auto &[port, sig] : connections_) {
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for (auto &chunk : sig.chunks()) {
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if (!chunk.wire)
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continue;
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module->buf_norm_connect_index[chunk.wire].insert(this);
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}
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}
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if (module && module->design && module->design->flagBufferedNormalized) {
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if (bufnorm_handle_setPort(portname, signal, conn_it))
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return;
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}
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}
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conn_it->second = std::move(signal);
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conn_it->second = std::move(signal);
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}
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void RTLIL::Design::add(RTLIL::Module *module)
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