diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt
index 60425fed9..c63218ae1 100644
--- a/techlibs/xilinx/xc7_xcu_brams.txt
+++ b/techlibs/xilinx/xc7_xcu_brams.txt
@@ -77,7 +77,25 @@ endbram
 # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
 
 match $__XILINX_RAMB36_SDP
-  attribute !ram_style ram_style=block ram_block
+  attribute !ram_style
+  attribute !logic_block
+  min bits 1024
+  min efficiency 5
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB36_SDP
+  attribute ram_style=block ram_block
+  attribute !logic_block
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB18_SDP
+  attribute !ram_style
   attribute !logic_block
   min bits 1024
   min efficiency 5
@@ -87,7 +105,15 @@ match $__XILINX_RAMB36_SDP
 endmatch
 
 match $__XILINX_RAMB18_SDP
-  attribute !ram_style ram_style=block ram_block
+  attribute ram_style=block ram_block
+  attribute !logic_block
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB36_TDP
+  attribute !ram_style
   attribute !logic_block
   min bits 1024
   min efficiency 5
@@ -97,7 +123,15 @@ match $__XILINX_RAMB18_SDP
 endmatch
 
 match $__XILINX_RAMB36_TDP
-  attribute !ram_style ram_style=block ram_block
+  attribute ram_style=block ram_block
+  attribute !logic_block
+  shuffle_enable B
+  make_transp
+  or_next_if_better
+endmatch
+
+match $__XILINX_RAMB18_TDP
+  attribute !ram_style
   attribute !logic_block
   min bits 1024
   min efficiency 5
@@ -107,10 +141,8 @@ match $__XILINX_RAMB36_TDP
 endmatch
 
 match $__XILINX_RAMB18_TDP
-  attribute !ram_style ram_style=block ram_block
+  attribute ram_style=block ram_block
   attribute !logic_block
-  min bits 1024
-  min efficiency 5
   shuffle_enable B
   make_transp
 endmatch
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index 362d33229..b6e105854 100644
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory
 synth_xilinx -top sync_ram_sdp
 cd sync_ram_sdp
 select -assert-count 0 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
+setattr -set ram_style "block" m:memory
+dump m:*
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1