mirror of
https://github.com/YosysHQ/yosys
synced 2025-05-14 11:14:44 +00:00
design: ensure all_modules outlives pass when building WITH_PYTHON
This commit is contained in:
parent
6900818105
commit
586fa033a6
1 changed files with 7 additions and 1 deletions
|
@ -23,11 +23,17 @@
|
||||||
|
|
||||||
YOSYS_NAMESPACE_BEGIN
|
YOSYS_NAMESPACE_BEGIN
|
||||||
|
|
||||||
|
// TODO refactor such scattered program state
|
||||||
std::map<std::string, RTLIL::Design*> saved_designs;
|
std::map<std::string, RTLIL::Design*> saved_designs;
|
||||||
std::vector<RTLIL::Design*> pushed_designs;
|
std::vector<RTLIL::Design*> pushed_designs;
|
||||||
|
|
||||||
struct DesignPass : public Pass {
|
struct DesignPass : public Pass {
|
||||||
DesignPass() : Pass("design", "save, restore and reset current design") { }
|
DesignPass() : Pass("design", "save, restore and reset current design") {
|
||||||
|
#ifdef WITH_PYTHON
|
||||||
|
// Ensure the index to outlive this pass so that we can free saved designs
|
||||||
|
(void)RTLIL::Module::get_all_modules();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
~DesignPass() override {
|
~DesignPass() override {
|
||||||
for (auto &it : saved_designs)
|
for (auto &it : saved_designs)
|
||||||
delete it.second;
|
delete it.second;
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue