From 586fa033a6721400d7a9c0e3b68e6a3d1a6ab3f0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Emil=20Ji=C5=99=C3=AD=20Tywoniak?= <emil.tywoniak@gmail.com>
Date: Sat, 10 May 2025 17:19:51 +0200
Subject: [PATCH] design: ensure all_modules outlives pass when building
 WITH_PYTHON

---
 passes/cmds/design.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index efc72dfb7..9f627ab04 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -23,11 +23,17 @@
 
 YOSYS_NAMESPACE_BEGIN
 
+// TODO refactor such scattered program state
 std::map<std::string, RTLIL::Design*> saved_designs;
 std::vector<RTLIL::Design*> pushed_designs;
 
 struct DesignPass : public Pass {
-	DesignPass() : Pass("design", "save, restore and reset current design") { }
+	DesignPass() : Pass("design", "save, restore and reset current design") {
+#ifdef WITH_PYTHON
+		// Ensure the index to outlive this pass so that we can free saved designs
+		(void)RTLIL::Module::get_all_modules();
+#endif
+	}
 	~DesignPass() override {
 		for (auto &it : saved_designs)
 			delete it.second;