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Merge 2ed89e02da into 9d0cdb8551

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Dhaval 2026-05-23 13:07:47 +08:00 • committed by GitHub
commit 57eac85347
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2 changed files with 26 additions and 2 deletions
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17
backends/verilog/verilog_backend.cc
View file

@ -387,14 +387,31 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
f << "{0{1'b0}}"; f << "{0{1'b0}}";
return; return;
} }
if (sig.is_fully_const() && GetSize(sig) > 8192) {
f << stringf("{ ");
int i = 0;
auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
dump_const(f, it->data, 1, 0);
if (it != chunks.rbegin())
f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
}
f << stringf(" }");
return;
}
if (sig.is_chunk()) { if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk()); dump_sigchunk(f, sig.as_chunk());
} else { } else {
f << stringf("{ "); f << stringf("{ ");
int i = 0;
auto chunks = sig.chunks(); auto chunks = sig.chunks();
for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) { for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
if (it != chunks.rbegin()) if (it != chunks.rbegin())
f << stringf(", "); f << stringf(", ");
if (i++ % 20 == 19)
f << stringf("\n");
dump_sigchunk(f, *it, true); dump_sigchunk(f, *it, true);
} }
f << stringf(" }"); f << stringf(" }");

11
frontends/verific/verific.cc
View file

@ -109,6 +109,7 @@ int verific_verbose;
bool verific_import_pending; bool verific_import_pending;
string verific_error_msg; string verific_error_msg;
int verific_sva_fsm_limit; int verific_sva_fsm_limit;
bool verific_no_split_complex_ports = false; // disable splitting of complex ports
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
vector<string> verific_incdirs, verific_libdirs, verific_libexts; vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@ -3061,8 +3062,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty()) if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg); log_error("%s\n", verific_error_msg);
for (auto nl : nl_todo) if (!verific_no_split_complex_ports)
nl.second->ChangePortBusStructures(1 /* hierarchical */); for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
VerificExtNets worker; VerificExtNets worker;
for (auto nl : nl_todo) for (auto nl : nl_todo)
@ -3697,6 +3699,11 @@ struct VerificPass : public Pass {
break; break;
} }
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
goto check_error;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{ {