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https://github.com/YosysHQ/yosys
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Merge 5ad9e4cacc into a80462f27f
This commit is contained in:
Priit Laes
GitHub
commit
575b1cde26
5 changed files with 204 additions and 1 deletions
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@ -11,3 +11,4 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v))
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65
techlibs/gowin/dsp_map.v
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65
techlibs/gowin/dsp_map.v
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@ -0,0 +1,65 @@
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module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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wire [8:0] soa;
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wire [8:0] sob;
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MULT9X9 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.SIA(8'b0),
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.SIB(8'b0),
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.ASIGN(A_SIGNED),
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.BSIGN(B_SIGNED),
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.ASEL(1'b0),
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.BSEL(1'b0),
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.SOA(soa),
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.SOB(sob),
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.DOUT(Y)
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);
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endmodule
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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wire [17:0] soa;
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wire [17:0] sob;
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MULT18X18 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.SIA(18'b0),
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.SIB(18'b0),
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.ASIGN(A_SIGNED),
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.BSIGN(B_SIGNED),
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.ASEL(1'b0),
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.BSEL(1'b0),
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.SOA(soa),
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.SOB(sob),
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.DOUT(Y)
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);
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endmodule
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module \$__MUL36X36 (input [35:0] A, input [35:0] B, output [72:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 72;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT36X36 _TECHMAP_REPLACE_ (
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.A(A),
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.B(B),
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.ASIGN(A_SIGNED),
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.BSIGN(B_SIGNED),
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.DOUT(Y)
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);
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endmodule
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@ -91,13 +91,16 @@ struct SynthGowinPass : public ScriptPass
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log(" The following families are supported:\n");
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log(" 'gw1n', 'gw2a', 'gw5a'.\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not infer DSP multipliers.\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, vout_file, json_file, family;
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bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu, no_rw_check;
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bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads, noalu, no_rw_check, nodsp;
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void clear_flags() override
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{
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@ -115,6 +118,7 @@ struct SynthGowinPass : public ScriptPass
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noiopads = false;
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noalu = false;
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no_rw_check = false;
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nodsp = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -193,6 +197,10 @@ struct SynthGowinPass : public ScriptPass
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no_rw_check = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -208,6 +216,24 @@ struct SynthGowinPass : public ScriptPass
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log_pop();
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}
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// DSP mapping rules for mul2dsp
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struct DSPRule {
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int a_maxwidth;
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int b_maxwidth;
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int a_minwidth;
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int b_minwidth;
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std::string prim;
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};
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// gw1n and gw2a
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const std::vector<DSPRule> dsp_rules = {
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{36, 36, 18, 18, "$__MUL36X36"},
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{18, 18, 10, 4, "$__MUL18X18"},
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{18, 18, 4, 10, "$__MUL18X18"},
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{ 9, 9, 4, 4, "$__MUL9X9"},
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};
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// TODO: gw5a (MULT12X12, MULT27x36)
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void script() override
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{
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std::string no_rw_check_opt = "";
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@ -233,6 +259,23 @@ struct SynthGowinPass : public ScriptPass
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if (check_label("coarse"))
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{
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if (help_mode)
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{
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
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run("techmap -map +/gowin/dsp_map.v [...]", "(unless -nodsp)");
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} else if (!nodsp) {
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if (family == "gw1n" || family == "gw2a")
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{
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for (const auto &rule : dsp_rules)
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{
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run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
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rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim.c_str()));
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run("chtype -set $mul t:$__soft_mul");
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}
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run("techmap -map +/gowin/dsp_map.v");
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}
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}
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run("synth -run coarse" + no_rw_check_opt);
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}
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47
tests/arch/gowin/mul_gw1n.ys
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47
tests/arch/gowin/mul_gw1n.ys
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@ -0,0 +1,47 @@
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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# equivalence checking is somewhat slow (and missing simulation models)
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synth_gowin -family gw1n
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT9X9
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# XXX: Whats's `top/x_IBUF_I_O_MULT9X9_A_A_GND_G` ??
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# select -assert-none t:IBUF t:OBUF t:MULT9X9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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synth_gowin -family gw1n
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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# XXX: top/x_IBUF_I_O_MULT18X18_A_A_GND_G ???
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# select -assert-none t:IBUF t:OBUF t:MULT18X18 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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# XXX: top/x_IBUF_I_O_MULT36X36_A_A_GND_G
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# select -assert-none t:IBUF t:OBUF t:MULT36X36 %% t:* %D
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# TODO: We end up with two 18x18 multipliers
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# design -reset
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# read_verilog ../common/mul.v
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# chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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# hierarchy -top top
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# proc
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# # equivalence checking is too slow here
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# synth_gowin
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# cd top # Constrain all select calls below inside the top module
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# select -assert-count 2 t:MULT18X18
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# select -assert-none t:IBUF t:OBUF t:MULT36X36 %% t:* %D
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47
tests/arch/gowin/mul_gw2a.ys
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47
tests/arch/gowin/mul_gw2a.ys
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@ -0,0 +1,47 @@
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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# equivalence checking is somewhat slow (and missing simulation models)
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT9X9
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# XXX: Whats's `top/x_IBUF_I_O_MULT9X9_A_A_GND_G` ??
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# select -assert-none t:IBUF t:OBUF t:MULT9X9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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# XXX: top/x_IBUF_I_O_MULT18X18_A_A_GND_G ???
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# select -assert-none t:IBUF t:OBUF t:MULT18X18 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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# XXX: top/x_IBUF_I_O_MULT36X36_A_A_GND_G
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# select -assert-none t:IBUF t:OBUF t:MULT36X36 %% t:* %D
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# TODO: We end up with two 18x18 multipliers
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# design -reset
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# read_verilog ../common/mul.v
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# chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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# hierarchy -top top
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# proc
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# # equivalence checking is too slow here
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# synth_gowin -family gw2a
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# cd top # Constrain all select calls below inside the top module
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# select -assert-count 2 t:MULT18X18
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# select -assert-none t:IBUF t:OBUF t:MULT36X36 %% t:* %D
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