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https://github.com/YosysHQ/yosys
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remove invalid tests, use scratchpad variable check.permissive
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parent
0601260bf2
commit
56d562299a
4 changed files with 1 additions and 70 deletions
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@ -1,29 +0,0 @@
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module d_ff_gates(d,clk,q,q_bar);
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input d,clk;
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output q, q_bar;
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wire n1,n2,n3,q_bar_n;
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wire cn,dn,n4,n5,n6;
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// First Latch
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not (n1,d);
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nand (n2,d,clk);
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nand (n3,n1,clk);
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nand (dn,q_bar_n,n2);
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nand (q_bar_n,dn,n3);
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// Second Latch
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not (cn,clk);
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not (n4,dn);
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nand (n5,dn,cn);
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nand (n6,n4,cn);
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nand (q,q_bar,n5);
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nand (q_bar,q,n6);
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endmodule
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@ -1,15 +0,0 @@
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module d_latch_gates(d,clk,q,q_bar);
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input d,clk;
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output q, q_bar;
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wire n1,n2,n3;
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not (n1,d);
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nand (n2,d,clk);
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nand (n3,n1,clk);
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nand (q,q_bar,n2);
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nand (q_bar,q,n3);
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endmodule
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@ -182,31 +182,6 @@ assign w2 = w1;
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assign out = w2;
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endmodule
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// test_intermout_bufrm_7_test.v
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module f15_test(in1, in2, out);
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input in1, in2;
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output out;
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// Y with cluster of f15_mybuf instances at the junction
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wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
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assign w1 = in1;
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assign w2 = w1;
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assign w5 = in2;
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assign w6 = w5;
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assign w10 = w9;
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assign out = w10;
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f15_mybuf _f15_mybuf0(w2, w3);
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f15_mybuf _f15_mybuf1(w3, w4);
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f15_mybuf _f15_mybuf2(w6, w7);
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f15_mybuf _f15_mybuf3(w7, w4);
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f15_mybuf _f15_mybuf4(w4, w8);
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f15_mybuf _f15_mybuf5(w8, w9);
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endmodule
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module f15_mybuf(in, out);
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input in;
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output out;
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@ -14,7 +14,7 @@ module test(
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reg [7:0] mem[3:254];
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assign rd[7:0] = mem[{ra, 1'b0}];
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assign rd[15:0] = mem[{ra, 1'b1}];
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assign rd[15:8] = mem[{ra, 1'b1}];
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initial begin
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mem[5] = 8'h12;
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