diff --git a/tests/asicworld/code_hdl_models_d_ff_gates.v b/tests/asicworld/code_hdl_models_d_ff_gates.v
deleted file mode 100644
index 8706f154c..000000000
--- a/tests/asicworld/code_hdl_models_d_ff_gates.v
+++ /dev/null
@@ -1,29 +0,0 @@
-module d_ff_gates(d,clk,q,q_bar);
-input d,clk;
-output q, q_bar;
-
-wire n1,n2,n3,q_bar_n;
-wire cn,dn,n4,n5,n6;
-
-// First Latch
-not (n1,d);
-
-nand (n2,d,clk);
-nand (n3,n1,clk);
-
-nand (dn,q_bar_n,n2);
-nand (q_bar_n,dn,n3);
-
-// Second Latch
-not (cn,clk);
-
-not (n4,dn);
-
-nand (n5,dn,cn);
-nand (n6,n4,cn);
-
-nand (q,q_bar,n5);
-nand (q_bar,q,n6);
-
-
-endmodule
diff --git a/tests/asicworld/code_hdl_models_d_latch_gates.v b/tests/asicworld/code_hdl_models_d_latch_gates.v
deleted file mode 100644
index 3f5f6b2bb..000000000
--- a/tests/asicworld/code_hdl_models_d_latch_gates.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module d_latch_gates(d,clk,q,q_bar);
-input d,clk;
-output q, q_bar;
-
-wire n1,n2,n3;
-
-not (n1,d);
-
-nand (n2,d,clk);
-nand (n3,n1,clk);
-
-nand (q,q_bar,n2);
-nand (q_bar,q,n3);
-
-endmodule
diff --git a/tests/hana/test_intermout.v b/tests/hana/test_intermout.v
index 88b91ee4d..4c231ab3a 100644
--- a/tests/hana/test_intermout.v
+++ b/tests/hana/test_intermout.v
@@ -182,31 +182,6 @@ assign w2 = w1;
 assign out = w2;
 endmodule
 
-
-// test_intermout_bufrm_7_test.v
-module f15_test(in1, in2, out);
-input in1, in2;
-output out;
-// Y with cluster of f15_mybuf instances at the junction
-
-wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
-assign w1 = in1;
-assign w2 = w1;
-assign w5 = in2;
-assign w6 = w5;
-assign w10 = w9;
-assign out = w10;
-
-f15_mybuf _f15_mybuf0(w2, w3);
-f15_mybuf _f15_mybuf1(w3, w4);
-
-f15_mybuf _f15_mybuf2(w6, w7);
-f15_mybuf _f15_mybuf3(w7, w4);
-
-f15_mybuf _f15_mybuf4(w4, w8);
-f15_mybuf _f15_mybuf5(w8, w9);
-endmodule
-
 module f15_mybuf(in, out);
 input in;
 output out;
diff --git a/tests/memories/wide_all.v b/tests/memories/wide_all.v
index f7bc3e5ce..1516b26fd 100644
--- a/tests/memories/wide_all.v
+++ b/tests/memories/wide_all.v
@@ -14,7 +14,7 @@ module test(
 reg [7:0] mem[3:254];
 
 assign rd[7:0] = mem[{ra, 1'b0}];
-assign rd[15:0] = mem[{ra, 1'b1}];
+assign rd[15:8] = mem[{ra, 1'b1}];
 
 initial begin
 	mem[5] = 8'h12;