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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

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This commit is contained in:
Eddie Hung 2019-07-16 14:18:36 -07:00
commit 569cd66764
4 changed files with 35 additions and 27 deletions
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2
techlibs/xilinx/cells_sim.v
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@ -516,7 +516,7 @@ module DSP48E1 (
if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value");
if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value");
`endif
Pr[42:0] <= Ar[24:0] * Br;
Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
end
generate

6
techlibs/xilinx/dsp_map.v
View file

@ -1,4 +1,4 @@
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y);
wire [47:0] P_48;
DSP48E1 #(
// Disable all registers
@ -20,8 +20,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
.PREG(0)
) _TECHMAP_REPLACE_ (
//Data path
.A({5'b0, A}),
.B(B),
.A({6'b0, A}),
.B({1'b0, B}),
.C(48'b0),
.D(24'b0),
.P(P_48),

6
techlibs/xilinx/synth_xilinx.cc
View file

@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
// The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
// Due to current limitations of mul2dsp, we are actually mapping as a 24x17
// unsigned multiply with MSBs set to 1'b0
if (!nodsp || help_mode)
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18");
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
run("alumacc");
run("share");