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read_verilog, ast: use unified locations in errors and simplify dependencies

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This commit is contained in:
Emil J. Tywoniak 2025-07-09 15:24:34 +02:00
parent 41d9a1b88e
commit 56058b3ed4
7 changed files with 16 additions and 23 deletions
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4
frontends/verilog/verilog_parser.y
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@ -200,7 +200,7 @@
if (type_node->range_left >= 0 && type_node->range_right >= 0) {
// type already restricts the range
if (range_node) {
err_at_ast(type_node->location, "integer/genvar types cannot have packed dimensions.");
err_at_loc(type_node->location, "integer/genvar types cannot have packed dimensions.");
}
else {
range_node = makeRange(type_node->location, type_node->range_left, type_node->range_right, false);
@ -217,7 +217,7 @@
}
}
if (!valid)
err_at_ast(type_node->location, "wire/reg/logic packed dimension must be of the form [<expr>:<expr>]");
err_at_loc(type_node->location, "wire/reg/logic packed dimension must be of the form [<expr>:<expr>]");
}
return range_node;