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ecp5 to use abc_map.v and _unmap.v

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This commit is contained in:
Eddie Hung 2019-08-20 18:59:03 -07:00
parent 4cd1d21bfe
commit 55acf3120f
7 changed files with 88 additions and 13 deletions
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3
techlibs/ecp5/Makefile.inc
View file

@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_map.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_unmap.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_model.v))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g_nowide.lut))

16
techlibs/ecp5/abc_5g.box
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@ -15,16 +15,16 @@ CCU2C 1 1 9 3
630 379 630 379 526 275 392 141 273 630 379 630 379 526 275 392 141 273
516 516 516 516 412 412 278 278 43 516 516 516 516 412 412 278 278 43
# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram) # Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
# Outputs: DO0, DO1, DO2, DO3 # Outputs: DO0, DO1, DO2, DO3
# name ID w/b ins outs # name ID w/b ins outs
TRELLIS_DPR16X4 2 0 14 4 $__ABC_RAM16X2_COMB 2 0 8 4
#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE #A0 A1 A2 A3 RAD0 RAD1 RAD2 RAD3
- - - - 141 379 275 379 - - - - - - 0 0 0 0 141 379 275 379
- - - - 141 379 275 379 - - - - - - 0 0 0 0 141 379 275 379
- - - - 141 379 275 379 - - - - - - 0 0 0 0 141 379 275 379
- - - - 141 379 275 379 - - - - - - 0 0 0 0 141 379 275 379
# Box 3 : PFUMX (MUX2) # Box 3 : PFUMX (MUX2)
# Outputs: Z # Outputs: Z

24
techlibs/ecp5/abc_map.v Normal file
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@ -0,0 +1,24 @@
// ---------------------------------------
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
wire [3:0] \$DO ;
\$__ABC_DPR16X4_SEQ #(
.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
) _TECHMAP_REPLACE_ (
.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
.RAD(RAD), .DO(\$DO )
);
\$__ABC_DPR16X4_COMB do (.A(\$DO ), .S(RAD), .Y(DO));
endmodule

18
techlibs/ecp5/abc_model.v Normal file
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@ -0,0 +1,18 @@
// ---------------------------------------
(* abc_box_id=2 *)
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
endmodule
module \$__ABC_DPR16X4_SEQ (
input [3:0] DI,
input [3:0] WAD,
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
endmodule

25
techlibs/ecp5/abc_unmap.v Normal file
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@ -0,0 +1,25 @@
// ---------------------------------------
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
assign Y = A;
endmodule
module \$__ABC_DPR16X4_SEQ (
input [3:0] DI,
input [3:0] WAD,
input WRE,
input WCK,
input [3:0] RAD,
output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
parameter [63:0] INITVAL = 64'h0000000000000000;
TRELLIS_DPR16X4 #(
.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
) _TECHMAP_REPLACE_ (
.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
.RAD(RAD), .DO(DO)
);
endmodule

7
techlibs/ecp5/cells_sim.v
View file

@ -107,11 +107,10 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule endmodule
// --------------------------------------- // ---------------------------------------
//(* abc_box_id=2 *)
module TRELLIS_DPR16X4 ( module TRELLIS_DPR16X4 (
(* abc_scc_break *) input [3:0] DI, input [3:0] DI,
(* abc_scc_break *) input [3:0] WAD, input [3:0] WAD,
(* abc_scc_break *) input WRE, input WRE,
input WCK, input WCK,
input [3:0] RAD, input [3:0] RAD,
output [3:0] DO output [3:0] DO

8
techlibs/ecp5/synth_ecp5.cc
View file

@ -278,12 +278,18 @@ struct SynthEcp5Pass : public ScriptPass
if (abc2 || help_mode) { if (abc2 || help_mode) {
run("abc", " (only if -abc2)"); run("abc", " (only if -abc2)");
} }
run("techmap -map +/ecp5/latches_map.v"); std::string techmap_args = "-map +/ecp5/latches_map.v";
if (abc9)
techmap_args += " -map +/ecp5/abc_map.v";
run("techmap " + techmap_args);
if (abc9) { if (abc9) {
run("read_verilog -icells -lib +/ecp5/abc_model.v");
if (nowidelut) if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200"); run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else else
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200"); run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
run("techmap -map +/ecp5/abc_unmap.v");
} else { } else {
if (nowidelut) if (nowidelut)
run("abc -lut 4 -dress"); run("abc -lut 4 -dress");