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Rename verific to import in tests and update README explanation

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This commit is contained in:
Akash Levy 2025-01-16 19:34:02 -08:00
parent 54c69f1fed
commit 53ed83fcac
4 changed files with 10 additions and 10 deletions
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6
tests/verific/blackbox_ql.ys
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@ -1,6 +1,6 @@
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
import -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
verific -sv <<EOF
import -sv <<EOF
module top (
input wire [19:0] a,
input wire [17:0] b,
@ -35,7 +35,7 @@ endmodule
EOF
verific -import top
import -import top
hierarchy -top top
synth_quicklogic -family qlf_k6n10f
select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324