From 53ed83fcac77b286950a46336e18cbeb022014cc Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 16 Jan 2025 19:34:02 -0800
Subject: [PATCH] Rename verific to import in tests and update README
 explanation

---
 tests/verific/README.md         | 4 ++--
 tests/verific/blackbox_empty.ys | 6 +++---
 tests/verific/blackbox_ql.ys    | 6 +++---
 tests/verific/setenv.ys         | 4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/tests/verific/README.md b/tests/verific/README.md
index 3badf8aeb..ebcbddc5e 100644
--- a/tests/verific/README.md
+++ b/tests/verific/README.md
@@ -2,6 +2,6 @@
 
 ## Disabled
 
-- `bounds`: checks top and bottom bound attributes, which are removed to avoid OpenSTA issues
+- `bounds`: relies on using Verific's VHDL frontend
 - `memory_semantics`: relies on initial values being retained, which we do not want
-- `rom_case`: relies on using Verific's VHDL frontend rather than GHDL
+- `rom_case`: relies on using Verific's VHDL frontend
diff --git a/tests/verific/blackbox_empty.ys b/tests/verific/blackbox_empty.ys
index fb407fe06..9e22e60fc 100644
--- a/tests/verific/blackbox_empty.ys
+++ b/tests/verific/blackbox_empty.ys
@@ -1,17 +1,17 @@
-verific -sv  <<EOF
+import -sv  <<EOF
 module TEST_CELL(input clk, input a, input b, output reg c);
 parameter PATH = "DEFAULT";
 endmodule
 EOF
 
-verific -sv <<EOF
+import -sv <<EOF
 module top(input clk, input a, input b, output c, output d);
 	TEST_CELL  #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
 	TEST_CELL  #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
 endmodule
 EOF
 
-verific -import top
+import -import top
 hierarchy -top top
 stat
 select -assert-count 2 t:TEST_CELL
diff --git a/tests/verific/blackbox_ql.ys b/tests/verific/blackbox_ql.ys
index 1c6d43587..e6093bae8 100644
--- a/tests/verific/blackbox_ql.ys
+++ b/tests/verific/blackbox_ql.ys
@@ -1,6 +1,6 @@
-verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v 
+import -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v 
 
-verific -sv <<EOF
+import -sv <<EOF
 module top (
     input  wire [19:0] a,
     input  wire [17:0] b,
@@ -35,7 +35,7 @@ endmodule
 
 EOF
 
-verific -import top
+import -import top
 hierarchy -top top
 synth_quicklogic -family qlf_k6n10f
 select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324
diff --git a/tests/verific/setenv.ys b/tests/verific/setenv.ys
index fa29000e6..1ae71fe85 100644
--- a/tests/verific/setenv.ys
+++ b/tests/verific/setenv.ys
@@ -1,4 +1,4 @@
 setenv filename case.sv
-verific -f -sv setenv.flist
-verific -import top
+import -f -sv setenv.flist
+import -import top
 select -assert-mod-count 1 top