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Rename verific to import in tests and update README explanation

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Akash Levy 2025-01-16 19:34:02 -08:00
parent 54c69f1fed
commit 53ed83fcac
4 changed files with 10 additions and 10 deletions
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tests/verific/README.md
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@ -2,6 +2,6 @@
## Disabled
- `bounds`: checks top and bottom bound attributes, which are removed to avoid OpenSTA issues
- `bounds`: relies on using Verific's VHDL frontend
- `memory_semantics`: relies on initial values being retained, which we do not want
- `rom_case`: relies on using Verific's VHDL frontend rather than GHDL
- `rom_case`: relies on using Verific's VHDL frontend