3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-11 12:11:27 +00:00

rtlil: add roundtrip test for design -stash and design -save, fix #5321

This commit is contained in:
Emil J. Tywoniak 2025-09-02 19:56:28 +02:00
parent c12b485135
commit 4fb0db4d69
3 changed files with 12 additions and 3 deletions

View file

@ -5855,6 +5855,7 @@ RTLIL::CaseRule *RTLIL::CaseRule::clone() const
RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
new_caserule->compare = compare;
new_caserule->actions = actions;
new_caserule->attributes = attributes;
for (auto &it : switches)
new_caserule->switches.push_back(it->clone());
return new_caserule;