From 4fb0db4d693463b9eb1013769fd648d3c25c435b Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Tue, 2 Sep 2025 19:56:28 +0200
Subject: [PATCH] rtlil: add roundtrip test for design -stash and design -save,
 fix #5321

---
 kernel/rtlil.cc                   | 1 +
 tests/rtlil/roundtrip-design.sh   | 8 ++++++++
 tests/rtlil/roundtrip-text.ref.il | 6 +++---
 3 files changed, 12 insertions(+), 3 deletions(-)
 create mode 100644 tests/rtlil/roundtrip-design.sh

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 0250346d1..4e07a473d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -5855,6 +5855,7 @@ RTLIL::CaseRule *RTLIL::CaseRule::clone() const
 	RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
 	new_caserule->compare = compare;
 	new_caserule->actions = actions;
+	new_caserule->attributes = attributes;
 	for (auto &it : switches)
 		new_caserule->switches.push_back(it->clone());
 	return new_caserule;
diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh
new file mode 100644
index 000000000..beacddd8f
--- /dev/null
+++ b/tests/rtlil/roundtrip-design.sh
@@ -0,0 +1,8 @@
+set -euo pipefail
+YS=../../yosys
+
+$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-push.tmp.il; design -push; design -pop; write_rtlil roundtrip-design-pop.tmp.il"
+diff roundtrip-design-push.tmp.il roundtrip-design-pop.tmp.il
+
+$YS -p "read_verilog -sv everything.v; write_rtlil roundtrip-design-save.tmp.il; design -save foo; design -load foo; write_rtlil roundtrip-design-load.tmp.il"
+diff roundtrip-design-save.tmp.il roundtrip-design-load.tmp.il
diff --git a/tests/rtlil/roundtrip-text.ref.il b/tests/rtlil/roundtrip-text.ref.il
index d67cb3626..cc45f53dd 100644
--- a/tests/rtlil/roundtrip-text.ref.il
+++ b/tests/rtlil/roundtrip-text.ref.il
@@ -203,7 +203,7 @@ module \zzz
     connect \B \B
     connect \Y $add$everything.v:21$2_Y
   end
-  attribute \src "everything.v:19.3-24.10"
+  attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10"
   attribute \full_case 1
   cell $eq $procmux$8_CMP0
     parameter \A_SIGNED 0
@@ -215,7 +215,7 @@ module \zzz
     connect \B 4'0001
     connect \Y $procmux$8_CMP
   end
-  attribute \src "everything.v:19.3-24.10"
+  attribute \src "everything.v:21.17-21.17|everything.v:19.3-24.10"
   attribute \full_case 1
   cell $pmux $procmux$7
     parameter \WIDTH 9
@@ -225,7 +225,7 @@ module \zzz
     connect \S { $procmux$9_CMP $procmux$8_CMP }
     connect \Y $procmux$7_Y
   end
-  attribute \src "everything.v:19.3-24.10"
+  attribute \src "everything.v:19.19-19.19|everything.v:19.3-24.10"
   attribute \full_case 1
   cell $logic_not $procmux$9_CMP0
     parameter \A_SIGNED 0