From 5643c1b8c5fbe1a31fcb4027ddbe096e74439cbf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Feb 2020 08:34:13 -0800
Subject: [PATCH 01/46] abc9_ops: -prep_lut and -write_lut to auto-generate LUT
 library

---
 passes/techmap/abc9.cc          | 36 ++++++++++++--
 passes/techmap/abc9_ops.cc      | 85 +++++++++++++++++++++++++++++++--
 techlibs/xilinx/cells_sim.v     | 83 ++++++++++++++++++++++++++++++++
 techlibs/xilinx/synth_xilinx.cc |  6 +--
 4 files changed, 200 insertions(+), 10 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 5ae2fb22a..0e2ca80c7 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -145,6 +145,11 @@ struct Abc9Pass : public ScriptPass
 		log("        generate netlist using luts. Use the specified costs for luts with 1,\n");
 		log("        2, 3, .. inputs.\n");
 		log("\n");
+		log("    -maxlut <width>\n");
+		log("        when auto-generating the lut library, discard all luts equal to or\n");
+		log("        greater than this size (applicable when neither -lut nor -luts is\n");
+		log("        specified).\n");
+		log("\n");
 		log("    -dff\n");
 		log("        also pass $_ABC9_FF_ cells through to ABC. modules with many clock\n");
 		log("        domains are marked as such and automatically partitioned by ABC.\n");
@@ -175,6 +180,8 @@ struct Abc9Pass : public ScriptPass
 
 	std::stringstream exe_cmd;
 	bool dff_mode, cleanup;
+	bool lut_mode;
+	int maxlut;
 	std::string box_file;
 
 	void clear_flags() YS_OVERRIDE
@@ -183,6 +190,8 @@ struct Abc9Pass : public ScriptPass
 		exe_cmd << "abc9_exe";
 		dff_mode = false;
 		cleanup = true;
+		lut_mode = false;
+		maxlut = 0;
 		box_file.clear();
 	}
 
@@ -204,9 +213,11 @@ struct Abc9Pass : public ScriptPass
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
 			if ((arg == "-exe" || arg == "-script" || arg == "-D" ||
-						/* arg == "-S" || */ arg == "-lut" || arg == "-luts" ||
+						/*arg == "-S" ||*/ arg == "-lut" || arg == "-luts" ||
 						/*arg == "-box" ||*/ arg == "-W") &&
 					argidx+1 < args.size()) {
+				if (arg == "-lut" || arg == "-luts")
+					lut_mode = true;
 				exe_cmd << " " << arg << " " << args[++argidx];
 				continue;
 			}
@@ -228,6 +239,10 @@ struct Abc9Pass : public ScriptPass
 				box_file = args[++argidx];
 				continue;
 			}
+			if (arg == "-maxlut" && argidx+1 < args.size()) {
+				maxlut = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (arg == "-run" && argidx+1 < args.size()) {
 				size_t pos = args[argidx+1].find(':');
 				if (pos == std::string::npos)
@@ -240,6 +255,9 @@ struct Abc9Pass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
+		if (maxlut && lut_mode)
+			log_cmd_error("abc9 '-maxlut' option only applicable without '-lut' nor '-luts'.\n");
+
 		log_assert(design);
 		if (design->selected_modules().empty()) {
 			log_warning("No modules selected for ABC9 techmapping.\n");
@@ -263,6 +281,10 @@ struct Abc9Pass : public ScriptPass
 				run("abc9_ops -mark_scc -prep_delays -prep_xaiger [-dff]", "(option for -dff)");
 			else
 				run("abc9_ops -mark_scc -prep_delays -prep_xaiger" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
+			if (help_mode)
+				run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
+			else if (!lut_mode)
+				run(stringf("abc9_ops -prep_lut %d", maxlut));
 			run("select -set abc9_holes A:abc9_holes");
 			run("flatten -wb @abc9_holes");
 			run("techmap @abc9_holes");
@@ -276,9 +298,10 @@ struct Abc9Pass : public ScriptPass
 		if (check_label("map")) {
 			if (help_mode) {
 				run("foreach module in selection");
+				run("    abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
 				run("    abc9_ops -write_box [<value from -box>|(null)] <abc-temp-dir>/input.box");
 				run("    write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
-				run("    abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box");
+				run("    abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box");
 				run("    read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
 				run("    abc9_ops -reintegrate");
 			}
@@ -304,6 +327,8 @@ struct Abc9Pass : public ScriptPass
 						tempdir_name[0] = tempdir_name[4] = '_';
 					tempdir_name = make_temp_dir(tempdir_name);
 
+					if (!lut_mode)
+						run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
 					if (box_file.empty())
 						run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
 					else
@@ -319,7 +344,12 @@ struct Abc9Pass : public ScriptPass
 							active_design->scratchpad_get_int("write_xaiger.num_inputs"),
 							num_outputs);
 					if (num_outputs) {
-						run(stringf("%s -cwd %s -box %s/input.box", exe_cmd.str().c_str(), tempdir_name.c_str(), tempdir_name.c_str()));
+						std::string abc9_exe_cmd;
+						abc9_exe_cmd += stringf("%s -cwd %s", exe_cmd.str().c_str(), tempdir_name.c_str());
+						if (!lut_mode)
+							abc9_exe_cmd += stringf(" -lut %s/input.lut", tempdir_name.c_str());
+						abc9_exe_cmd += stringf(" -box %s/input.box", tempdir_name.c_str());
+						run(abc9_exe_cmd);
 						run(stringf("read_aiger -xaiger -wideports -module_name %s$abc9 -map %s/input.sym %s/output.aig", log_id(mod), tempdir_name.c_str(), tempdir_name.c_str()));
 						run("abc9_ops -reintegrate");
 					}
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 54605f90e..cf6d5eabb 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -562,6 +562,56 @@ void prep_delays(RTLIL::Design *design)
 	design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
 }
 
+void prep_lut(RTLIL::Design *design, int maxlut)
+{
+	std::stringstream ss;
+	std::vector<std::pair<int, std::string>> table;
+	for (auto module : design->modules()) {
+		auto it = module->attributes.find(ID(abc9_lut));
+		if (it == module->attributes.end())
+			continue;
+		SigBit o;
+		std::vector<int> specify;
+		for (auto cell : module->cells()) {
+			if (cell->type != ID($specify2))
+				continue;
+			log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
+			log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
+			SigBit d = cell->getPort(ID(DST));
+			if (o == SigBit())
+				o = d;
+			else
+				log_assert(o == d);
+			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
+			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+			specify.push_back(std::max(rise_max,fall_max));
+		}
+		if (maxlut && GetSize(specify) > maxlut)
+			continue;
+		std::sort(specify.begin(), specify.end());
+		ss.str("");
+		ss << "# " << module->name.str() << std::endl;
+		ss << GetSize(specify) << " " << it->second.as_int();
+		for (auto i : specify)
+			ss << " " << i;
+		ss << std::endl;
+		table.emplace_back(GetSize(specify), ss.str());
+	}
+	// ABC expects ascending size
+	std::sort(table.begin(), table.end());
+	ss.str("");
+	for (auto &i : table)
+		ss << i.second;
+	design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
+}
+
+void write_lut(RTLIL::Module *module, const std::string &dst) {
+	std::ofstream ofs(dst);
+	log_assert(ofs.is_open());
+	ofs << module->design->scratchpad_get_string("abc9_ops.lut_library");
+	ofs.close();
+}
+
 void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
 	std::ofstream ofs(dst);
 	log_assert(ofs.is_open());
@@ -1002,6 +1052,12 @@ struct Abc9OpsPass : public Pass {
 		log("        compute the clock domain and initial value of each flop in the design.\n");
 		log("        process the '$holes' module to support clock-enable functionality.\n");
 		log("\n");
+		log("    -prep_lut <maxlut>\n");
+		log("        pre-compute the lut library.\n");
+		log("\n");
+		log("    -write_lut <dst>\n");
+		log("        TODO.\n");
+		log("\n");
 		log("    -write_box (<src>|(null)) <dst>\n");
 		log("        copy the existing box file from <src> (skip if '(null)') and append any\n");
 		log("        new box definitions.\n");
@@ -1021,8 +1077,11 @@ struct Abc9OpsPass : public Pass {
 		bool mark_scc_mode = false;
 		bool prep_dff_mode = false;
 		bool prep_xaiger_mode = false;
+		bool prep_lut_mode = false;
 		bool reintegrate_mode = false;
 		bool dff_mode = false;
+		std::string write_lut_dst;
+		int maxlut = 0;
 		std::string write_box_src, write_box_dst;
 
 		size_t argidx;
@@ -1048,6 +1107,19 @@ struct Abc9OpsPass : public Pass {
 				prep_delays_mode = true;
 				continue;
 			}
+			if (arg == "-prep_lut" && argidx+1 < args.size()) {
+				prep_lut_mode = true;
+				maxlut = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (arg == "-write_lut" && argidx+1 < args.size()) {
+				write_lut_dst = args[++argidx];
+				rewrite_filename(write_lut_dst);
+				continue;
+			}
+			if (arg == "-maxlut" && argidx+1 < args.size()) {
+				continue;
+			}
 			if (arg == "-write_box" && argidx+2 < args.size()) {
 				write_box_src = args[++argidx];
 				write_box_dst = args[++argidx];
@@ -1067,16 +1139,21 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || !write_box_src.empty() || reintegrate_mode))
-			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff}, -write_box, -reintegrate must be specified.\n");
+		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
+			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut}, -write_{lut,box}, -reintegrate must be specified.\n");
 
 		if (dff_mode && !prep_xaiger_mode)
 			log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
 
+		if (maxlut && !write_lut_dst.empty())
+			log_cmd_error("'-maxlut' option is only relevant for -prep_lut.\n");
+
 		if (check_mode)
 			check(design);
 		if (prep_delays_mode)
 			prep_delays(design);
+		if (prep_lut_mode)
+			prep_lut(design, maxlut);
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
@@ -1090,7 +1167,9 @@ struct Abc9OpsPass : public Pass {
 			if (!design->selected_whole_module(mod))
 				log_error("Can't handle partially selected module %s!\n", log_id(mod));
 
-			if (!write_box_src.empty())
+			if (!write_lut_dst.empty())
+				write_lut(mod, write_lut_dst);
+			if (!write_box_dst.empty())
 				write_box(mod, write_box_src, write_box_dst);
 			if (mark_scc_mode)
 				mark_scc(mod);
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 4692eba33..a1fe56fa1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -162,32 +162,55 @@ module INV(
   assign O = !I;
 endmodule
 
+(* abc9_lut=1 *)
 module LUT1(output O, input I0);
   parameter [1:0] INIT = 0;
   assign O = I0 ? INIT[1] : INIT[0];
+  specify
+    (I0 => O) = 127;
+  endspecify
 endmodule
 
+(* abc9_lut=2 *)
 module LUT2(output O, input I0, I1);
   parameter [3:0] INIT = 0;
   wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
   assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 238;
+    (I1 => O) = 127;
+  endspecify
 endmodule
 
+(* abc9_lut=3 *)
 module LUT3(output O, input I0, I1, I2);
   parameter [7:0] INIT = 0;
   wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
   assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 407;
+    (I1 => O) = 238;
+    (I2 => O) = 127;
+  endspecify
 endmodule
 
+(* abc9_lut=3 *)
 module LUT4(output O, input I0, I1, I2, I3);
   parameter [15:0] INIT = 0;
   wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
   assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 472;
+    (I1 => O) = 407;
+    (I2 => O) = 238;
+    (I3 => O) = 127;
+  endspecify
 endmodule
 
+(* abc9_lut=3 *)
 module LUT5(output O, input I0, I1, I2, I3, I4);
   parameter [31:0] INIT = 0;
   wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
@@ -195,8 +218,16 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
   assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 631;
+    (I1 => O) = 472;
+    (I2 => O) = 407;
+    (I3 => O) = 238;
+    (I4 => O) = 127;
+  endspecify
 endmodule
 
+(* abc9_lut=5 *)
 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
   parameter [63:0] INIT = 0;
   wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
@@ -205,6 +236,14 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
   wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
   wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
   assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 642;
+    (I1 => O) = 631;
+    (I2 => O) = 472;
+    (I3 => O) = 407;
+    (I4 => O) = 238;
+    (I5 => O) = 127;
+  endspecify
 endmodule
 
 module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
@@ -223,6 +262,50 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule
 
+(* abc9_lut=10 *)
+module $__ABC9_LUT7(output O, input I0, I1, I2, I3, I4, I5, I6);
+  parameter [127:0] INIT = 0;
+  wire [63: 0] s6 = I6 ? INIT[127:64] : INIT[63: 0];
+  wire [31: 0] s5 = I5 ?    s6[63:32] :   s6[31: 0];
+  wire [15: 0] s4 = I4 ?    s5[31:16] :   s5[15: 0];
+  wire [ 7: 0] s3 = I3 ?    s4[15: 8] :   s4[ 7: 0];
+  wire [ 3: 0] s2 = I2 ?    s3[ 7: 4] :   s3[ 3: 0];
+  wire [ 1: 0] s1 = I1 ?    s2[ 3: 2] :   s2[ 1: 0];
+  assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 1028;
+    (I1 => O) = 1017;
+    (I2 => O) =  858;
+    (I3 => O) =  793;
+    (I4 => O) =  624;
+    (I5 => O) =  513;
+    (I6 => O) =  464;
+  endspecify
+endmodule
+
+(* abc9_lut=20 *)
+module $__ABC9_LUT8(output O, input I0, I1, I2, I3, I4, I5, I6, I7);
+  parameter [255:0] INIT = 0;
+  wire [127: 0] s7 = I7 ? INIT[255:128] : INIT[127: 0];
+  wire [ 63: 0] s6 = I6 ?   s7[127:63]  :   s7[ 64: 0];
+  wire [ 31: 0] s5 = I5 ?   s6[ 63:32]  :   s6[ 31: 0];
+  wire [ 15: 0] s4 = I4 ?   s5[ 31:16]  :   s5[ 15: 0];
+  wire [  7: 0] s3 = I3 ?   s4[ 15: 8]  :   s4[  7: 0];
+  wire [  3: 0] s2 = I2 ?   s3[  7: 4]  :   s3[  3: 0];
+  wire [  1: 0] s1 = I1 ?   s2[  3: 2]  :   s2[  1: 0];
+  assign O = I0 ? s1[1] : s1[0];
+  specify
+    (I0 => O) = 1149;
+    (I1 => O) = 1138;
+    (I2 => O) =  979;
+    (I3 => O) =  914;
+    (I4 => O) =  745;
+    (I5 => O) =  634;
+    (I6 => O) =  585;
+    (I7 => O) =  468;
+  endspecify
+endmodule
+
 module MUXCY(output O, input CI, DI, S);
   assign O = S ? CI : DI;
 endmodule
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a6b422b83..4614a2bf9 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -354,7 +354,7 @@ struct SynthXilinxPass : public ScriptPass
 			std::string read_args;
 			if (vpr)
 				read_args += " -D_EXPLICIT_CARRY";
-			read_args += " -lib +/xilinx/cells_sim.v";
+			read_args += " -lib -specify +/xilinx/cells_sim.v";
 			run("read_verilog" + read_args);
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");
@@ -627,9 +627,7 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
 				if (nowidelut)
-					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
-				else
-					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+					abc9_opts += stringf(" -maxlut %d", lut_size_s);
 				if (dff_mode)
 					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);

From 74f49b1f55e08c9939c9e0c8a1a5c0405f0d28c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Feb 2020 08:54:13 -0800
Subject: [PATCH 02/46] abc9_ops: -prep_box, to be called once

---
 passes/techmap/abc9.cc          | 13 ++---
 passes/techmap/abc9_ops.cc      | 86 ++++++++++++++++-----------------
 techlibs/xilinx/synth_xilinx.cc |  2 +-
 3 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 0e2ca80c7..fc82f0e5f 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -192,7 +192,7 @@ struct Abc9Pass : public ScriptPass
 		cleanup = true;
 		lut_mode = false;
 		maxlut = 0;
-		box_file.clear();
+		box_file = "(null)";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -285,6 +285,10 @@ struct Abc9Pass : public ScriptPass
 				run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
 			else if (!lut_mode)
 				run(stringf("abc9_ops -prep_lut %d", maxlut));
+			if (help_mode)
+				run("abc9_ops -prep_box [<-box>|(null)]");
+			else
+				run(stringf("abc9_ops -prep_box %s", box_file.c_str()));
 			run("select -set abc9_holes A:abc9_holes");
 			run("flatten -wb @abc9_holes");
 			run("techmap @abc9_holes");
@@ -299,7 +303,7 @@ struct Abc9Pass : public ScriptPass
 			if (help_mode) {
 				run("foreach module in selection");
 				run("    abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
-				run("    abc9_ops -write_box [<value from -box>|(null)] <abc-temp-dir>/input.box");
+				run("    abc9_ops -write_box <abc-temp-dir>/input.box");
 				run("    write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
 				run("    abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box");
 				run("    read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
@@ -329,10 +333,7 @@ struct Abc9Pass : public ScriptPass
 
 					if (!lut_mode)
 						run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
-					if (box_file.empty())
-						run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
-					else
-						run(stringf("abc9_ops -write_box %s %s/input.box", box_file.c_str(), tempdir_name.c_str()));
+					run(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
 					run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
 
 					int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cf6d5eabb..d08c42e3b 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -464,7 +464,6 @@ void prep_delays(RTLIL::Design *design)
 			cells.emplace_back(cell);
 		}
 
-		delays.clear();
 		for (auto cell : cells) {
 			RTLIL::Module* inst_module = module->design->module(cell->type);
 			log_assert(inst_module);
@@ -515,17 +514,6 @@ void prep_delays(RTLIL::Design *design)
 				}
 			}
 		}
-
-		std::stringstream ss;
-		bool first = true;
-		for (auto d : delays) {
-			if (first)
-				first = false;
-			else
-				ss << " ";
-			ss << d;
-		}
-		module->attributes[ID(abc9_delays)] = ss.str();
 	}
 
 	int flops_id = ABC9_FLOPS_BASE_ID;
@@ -559,7 +547,14 @@ void prep_delays(RTLIL::Design *design)
 		// Last input is 'abc9_ff.Q'
 		ss << " 0" << std::endl << std::endl;
 	}
-	design->scratchpad_set_string("abc9_ops.box.flops", ss.str());
+	design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
+
+	ss.str("");
+	for (const int d : delays) {
+		ss << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
+		ss << d << std::endl;
+	}
+	design->scratchpad_set_string("abc9_ops.box_library.delays", ss.str());
 }
 
 void prep_lut(RTLIL::Design *design, int maxlut)
@@ -612,33 +607,31 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 	ofs.close();
 }
 
-void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) {
-	std::ofstream ofs(dst);
-	log_assert(ofs.is_open());
+void prep_box(RTLIL::Design *design, const std::string &src)
+{
+	std::stringstream ss;
 
 	// Since ABC can only accept one box file, we have to copy
 	//   over the existing box file
 	if (src != "(null)") {
 		std::ifstream ifs(src);
-		ofs << ifs.rdbuf() << std::endl;
+		log_assert(ifs.is_open());
+		ss << ifs.rdbuf() << std::endl;
 		ifs.close();
 	}
 
-	ofs << module->design->scratchpad_get_string("abc9_ops.box.flops");
-
-	auto it = module->attributes.find(ID(abc9_delays));
-	if (it != module->attributes.end()) {
-		for (const auto &tok : split_tokens(it->second.decode_string())) {
-			int d = atoi(tok.c_str());
-			ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
-			ofs << d << std::endl;
-		}
-		module->attributes.erase(it);
-	}
+	ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
+	ss << design->scratchpad_get_string("abc9_ops.box_library.delays", ss.str());
+	design->scratchpad_set_string("abc9_ops.box_library", ss.str());
+}
 
+void write_box(RTLIL::Module *module, const std::string &dst) {
+	std::ofstream ofs(dst);
+	log_assert(ofs.is_open());
+	ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
+	// ABC expects at least one box
 	if (ofs.tellp() == 0)
 		ofs << "(dummy) 1 0 0 0";
-
 	ofs.close();
 }
 
@@ -1056,11 +1049,14 @@ struct Abc9OpsPass : public Pass {
 		log("        pre-compute the lut library.\n");
 		log("\n");
 		log("    -write_lut <dst>\n");
-		log("        TODO.\n");
+		log("        write the pre-computed lut library to <dst>.\n");
 		log("\n");
-		log("    -write_box (<src>|(null)) <dst>\n");
-		log("        copy the existing box file from <src> (skip if '(null)') and append any\n");
-		log("        new box definitions.\n");
+		log("    -prep_box <src>\n");
+		log("        pre-compute the box library. copy the existing box file from <src> (skip\n");
+		log("        if '(null)').\n");
+		log("\n");
+		log("    -write_box <dst>\n");
+		log("        write the pre-computed box library to <dst>.\n");
 		log("\n");
 		log("    -reintegrate\n");
 		log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
@@ -1082,7 +1078,7 @@ struct Abc9OpsPass : public Pass {
 		bool dff_mode = false;
 		std::string write_lut_dst;
 		int maxlut = 0;
-		std::string write_box_src, write_box_dst;
+		std::string prep_box_src, write_box_dst;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
@@ -1112,18 +1108,21 @@ struct Abc9OpsPass : public Pass {
 				maxlut = atoi(args[++argidx].c_str());
 				continue;
 			}
+			if (arg == "-maxlut" && argidx+1 < args.size()) {
+				continue;
+			}
 			if (arg == "-write_lut" && argidx+1 < args.size()) {
 				write_lut_dst = args[++argidx];
 				rewrite_filename(write_lut_dst);
 				continue;
 			}
-			if (arg == "-maxlut" && argidx+1 < args.size()) {
+			if (arg == "-prep_box" && argidx+1 < args.size()) {
+				prep_box_src = args[++argidx];
+				rewrite_filename(prep_box_src);
 				continue;
 			}
-			if (arg == "-write_box" && argidx+2 < args.size()) {
-				write_box_src = args[++argidx];
+			if (arg == "-write_box" && argidx+1 < args.size()) {
 				write_box_dst = args[++argidx];
-				rewrite_filename(write_box_src);
 				rewrite_filename(write_box_dst);
 				continue;
 			}
@@ -1139,21 +1138,20 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
-			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut}, -write_{lut,box}, -reintegrate must be specified.\n");
+		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !prep_box_src.empty() || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
+			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
 
 		if (dff_mode && !prep_xaiger_mode)
 			log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
 
-		if (maxlut && !write_lut_dst.empty())
-			log_cmd_error("'-maxlut' option is only relevant for -prep_lut.\n");
-
 		if (check_mode)
 			check(design);
 		if (prep_delays_mode)
 			prep_delays(design);
 		if (prep_lut_mode)
 			prep_lut(design, maxlut);
+		if (!prep_box_src.empty())
+			prep_box(design, prep_box_src);
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
@@ -1170,7 +1168,7 @@ struct Abc9OpsPass : public Pass {
 			if (!write_lut_dst.empty())
 				write_lut(mod, write_lut_dst);
 			if (!write_box_dst.empty())
-				write_box(mod, write_box_src, write_box_dst);
+				write_box(mod, write_box_dst);
 			if (mark_scc_mode)
 				mark_scc(mod);
 			if (prep_dff_mode)
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4614a2bf9..db39330ae 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -627,7 +627,7 @@ struct SynthXilinxPass : public ScriptPass
 				else
 					abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
 				if (nowidelut)
-					abc9_opts += stringf(" -maxlut %d", lut_size_s);
+					abc9_opts += stringf(" -maxlut %d", lut_size);
 				if (dff_mode)
 					abc9_opts += " -dff";
 				run("abc9" + abc9_opts);

From 3d6603792dbd36ccb572403815b78121a7ad80e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Feb 2020 09:18:08 -0800
Subject: [PATCH 03/46] abc9_ops: assert on $specify2 properties

---
 passes/techmap/abc9_ops.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index d08c42e3b..52beae421 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -572,7 +572,10 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 				continue;
 			log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
 			log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
+			SigBit s = cell->getPort(ID(SRC));
 			SigBit d = cell->getPort(ID(DST));
+			log_assert(s.wire->port_input);
+			log_assert(d.wire->port_output);
 			if (o == SigBit())
 				o = d;
 			else

From 0e7c55e2a73f47d7f179d434ba79dd9e2bf9045b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Feb 2020 11:38:49 -0800
Subject: [PATCH 04/46] Auto-generate .box/.lut files from specify blocks

---
 passes/techmap/abc9_ops.cc          | 157 +++++++++---
 techlibs/xilinx/Makefile.inc        |   3 -
 techlibs/xilinx/abc9_model.v        |  90 ++++++-
 techlibs/xilinx/abc9_xc7.box        | 384 ----------------------------
 techlibs/xilinx/abc9_xc7.lut        |  15 --
 techlibs/xilinx/abc9_xc7_nowide.lut |  10 -
 techlibs/xilinx/cells_sim.v         |  73 +++++-
 techlibs/xilinx/synth_xilinx.cc     |   2 +-
 8 files changed, 268 insertions(+), 466 deletions(-)
 delete mode 100644 techlibs/xilinx/abc9_xc7.box
 delete mode 100644 techlibs/xilinx/abc9_xc7.lut
 delete mode 100644 techlibs/xilinx/abc9_xc7_nowide.lut

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 52beae421..bbbbc45d0 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -23,9 +23,6 @@
 #include "kernel/utils.h"
 #include "kernel/celltypes.h"
 
-#define ABC9_FLOPS_BASE_ID 8000
-#define ABC9_DELAY_BASE_ID 9000
-
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
@@ -269,7 +266,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 		if (abc9_flop && !dff)
 			continue;
 
-		if ((inst_module && inst_module->attributes.count("\\abc9_box_id")) || abc9_flop) {
+		if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
 			auto r = box_ports.insert(cell->type);
 			if (r.second) {
 				// Make carry in the last PI, and carry out the last PO
@@ -350,7 +347,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 		log_assert(cell);
 
 		RTLIL::Module* box_module = design->module(cell->type);
-		if (!box_module || (!box_module->attributes.count("\\abc9_box_id") && !box_module->get_bool_attribute("\\abc9_flop")))
+		if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
 			continue;
 
 		cell->attributes["\\abc9_box_seq"] = box_count++;
@@ -431,7 +428,6 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design)
 {
-	std::set<int> delays;
 	pool<Module*> flops;
 	std::vector<Cell*> cells;
 	dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
@@ -459,7 +455,7 @@ void prep_delays(RTLIL::Design *design)
 				continue; // because all flop required times
 				          //   will be captured in the flop box
 			}
-			if (inst_module->attributes.count(ID(abc9_box_id)))
+			if (inst_module->attributes.count(ID(abc9_box)))
 				continue;
 			cells.emplace_back(cell);
 		}
@@ -481,13 +477,11 @@ void prep_delays(RTLIL::Design *design)
 						continue;
 					if (it->second.flags == 0) {
 						int delay = it->second.as_int();
-						delays.insert(delay);
 						requireds.emplace_back(delay);
 					}
 					else
 						for (const auto &tok : split_tokens(it->second.decode_string())) {
 							int delay = atoi(tok.c_str());
-							delays.insert(delay);
 							requireds.push_back(delay);
 						}
 				}
@@ -516,12 +510,13 @@ void prep_delays(RTLIL::Design *design)
 		}
 	}
 
-	int flops_id = ABC9_FLOPS_BASE_ID;
+	int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
 	std::stringstream ss;
 	for (auto flop_module : flops) {
 		int num_inputs = 0, num_outputs = 0;
 		for (auto port_name : flop_module->ports) {
 			auto wire = flop_module->wire(port_name);
+			log_assert(GetSize(wire) == 1);
 			if (wire->port_input) num_inputs++;
 			if (wire->port_output) num_outputs++;
 		}
@@ -529,11 +524,27 @@ void prep_delays(RTLIL::Design *design)
 
 		auto r = flop_module->attributes.insert(ID(abc9_box_id));
 		if (r.second)
-			r.first->second = flops_id++;
+			r.first->second = ++abc9_box_id;
 
 		ss << log_id(flop_module) << " " << r.first->second.as_int();
-		ss << " 1 " << num_inputs+1 << " " << num_outputs << std::endl;
+		ss << " " << (flop_module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+		ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+
+		ss << "#";
 		bool first = true;
+		for (auto port_name : flop_module->ports) {
+			auto wire = flop_module->wire(port_name);
+			if (!wire->port_input)
+				continue;
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			ss << log_id(wire);
+		}
+		ss << " abc9_ff.Q" << std::endl;
+
+		first = true;
 		for (auto port_name : flop_module->ports) {
 			auto wire = flop_module->wire(port_name);
 			if (!wire->port_input)
@@ -548,13 +559,7 @@ void prep_delays(RTLIL::Design *design)
 		ss << " 0" << std::endl << std::endl;
 	}
 	design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
-
-	ss.str("");
-	for (const int d : delays) {
-		ss << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
-		ss << d << std::endl;
-	}
-	design->scratchpad_set_string("abc9_ops.box_library.delays", ss.str());
+	design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
 }
 
 void prep_lut(RTLIL::Design *design, int maxlut)
@@ -610,22 +615,93 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 	ofs.close();
 }
 
-void prep_box(RTLIL::Design *design, const std::string &src)
+void prep_box(RTLIL::Design *design)
 {
 	std::stringstream ss;
+	ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
 
-	// Since ABC can only accept one box file, we have to copy
-	//   over the existing box file
-	if (src != "(null)") {
-		std::ifstream ifs(src);
-		log_assert(ifs.is_open());
-		ss << ifs.rdbuf() << std::endl;
-		ifs.close();
+	int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
+	for (auto module : design->modules()) {
+		auto it = module->attributes.find(ID(abc9_box));
+		if (it == module->attributes.end())
+			continue;
+		module->attributes.erase(it);
+		log_assert(!module->attributes.count(ID(abc9_box_id)));
+
+		dict<std::pair<SigBit,SigBit>, std::string> table;
+		std::vector<SigBit> inputs;
+		std::vector<SigBit> outputs;
+		for (auto port_name : module->ports) {
+			auto wire = module->wire(port_name);
+			if (wire->port_input)
+				for (int i = 0; i < GetSize(wire); i++)
+					inputs.emplace_back(wire, i);
+			if (wire->port_output)
+				for (int i = 0; i < GetSize(wire); i++)
+					outputs.emplace_back(wire, i);
+		}
+		for (auto cell : module->cells()) {
+			if (cell->type != ID($specify2))
+				continue;
+			auto src = cell->getPort(ID(SRC));
+			auto dst = cell->getPort(ID(DST));
+			for (const auto &c : src.chunks())
+				if (!c.wire->port_input)
+					log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+			for (const auto &c : dst.chunks())
+				if (!c.wire->port_output)
+					log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
+			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
+			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+			int max = std::max(rise_max,fall_max);
+			for (auto s : src)
+				for (auto d : dst) {
+					auto r = table.insert(std::make_pair(s,d));
+					log_assert(r.second);
+					r.first->second = std::to_string(max);
+				}
+		}
+		auto r = module->attributes.insert(ID(abc9_box_id));
+		log_assert(r.second);
+		r.first->second = ++abc9_box_id;
+		ss << log_id(module) << " " << abc9_box_id;
+		ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+		ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
+		bool first = true;
+		ss << "#";
+		for (const auto &i : inputs) {
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			if (GetSize(i.wire) == 1)
+				ss << log_id(i.wire);
+			else
+				ss << log_id(i.wire) << "[" << i.offset << "]";
+		}
+		ss << std::endl;
+		for (const auto &o : outputs) {
+			first = true;
+			for (const auto &i : inputs) {
+				if (first)
+					first = false;
+				else
+					ss << " ";
+				ss << table.at(std::make_pair(i,o), "-");
+			}
+			ss << " # ";
+			if (GetSize(o.wire) == 1)
+				ss << log_id(o.wire);
+			else
+				ss << log_id(o.wire) << "[" << o.offset << "]";
+			ss << std::endl;
+
+		}
+		ss << std::endl;
 	}
 
-	ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
-	ss << design->scratchpad_get_string("abc9_ops.box_library.delays", ss.str());
 	design->scratchpad_set_string("abc9_ops.box_library", ss.str());
+	design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
 }
 
 void write_box(RTLIL::Module *module, const std::string &dst) {
@@ -1049,14 +1125,15 @@ struct Abc9OpsPass : public Pass {
 		log("        process the '$holes' module to support clock-enable functionality.\n");
 		log("\n");
 		log("    -prep_lut <maxlut>\n");
-		log("        pre-compute the lut library.\n");
+		log("        pre-compute the lut library by analysing all modules marked with\n");
+		log("        (* abc9_lut=<area> *).\n");
 		log("\n");
 		log("    -write_lut <dst>\n");
 		log("        write the pre-computed lut library to <dst>.\n");
 		log("\n");
-		log("    -prep_box <src>\n");
-		log("        pre-compute the box library. copy the existing box file from <src> (skip\n");
-		log("        if '(null)').\n");
+		log("    -prep_box\n");
+		log("        pre-compute the box library by analysing all modules marked with\n");
+		log("        (* abc9_box *)\n");
 		log("\n");
 		log("    -write_box <dst>\n");
 		log("        write the pre-computed box library to <dst>.\n");
@@ -1077,11 +1154,12 @@ struct Abc9OpsPass : public Pass {
 		bool prep_dff_mode = false;
 		bool prep_xaiger_mode = false;
 		bool prep_lut_mode = false;
+		bool prep_box_mode = false;
 		bool reintegrate_mode = false;
 		bool dff_mode = false;
 		std::string write_lut_dst;
 		int maxlut = 0;
-		std::string prep_box_src, write_box_dst;
+		std::string write_box_dst;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
@@ -1119,9 +1197,8 @@ struct Abc9OpsPass : public Pass {
 				rewrite_filename(write_lut_dst);
 				continue;
 			}
-			if (arg == "-prep_box" && argidx+1 < args.size()) {
-				prep_box_src = args[++argidx];
-				rewrite_filename(prep_box_src);
+			if (arg == "-prep_box") {
+				prep_box_mode = true;
 				continue;
 			}
 			if (arg == "-write_box" && argidx+1 < args.size()) {
@@ -1141,7 +1218,7 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !prep_box_src.empty() || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
+		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
 			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
 
 		if (dff_mode && !prep_xaiger_mode)
@@ -1153,8 +1230,8 @@ struct Abc9OpsPass : public Pass {
 			prep_delays(design);
 		if (prep_lut_mode)
 			prep_lut(design, maxlut);
-		if (!prep_box_src.empty())
-			prep_box(design, prep_box_src);
+		if (prep_box_mode)
+			prep_box(design);
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index d07bae12a..9984290a6 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -57,9 +57,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_model.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.box))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7.lut))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_xc7_nowide.lut))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 782c53ab6..4373191ea 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -24,30 +24,49 @@
 //   Necessary to make these an atomic unit so that
 //   ABC cannot optimise just one of the MUXF7 away
 //   and expect to save on its delay
-(* abc9_box_id = 3, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
   assign O = S1 ? (S0 ? I3 : I2)
                 : (S0 ? I1 : I0);
+  specify
+    (I0 => O) = 294;
+    (I1 => O) = 297;
+    (I2 => O) = 311;
+    (I3 => O) = 317;
+    (S0 => O) = 390;
+    (S1 => O) = 273;
+  endspecify
 endmodule
 
 module \$__ABC9_FF_ (input D, output Q);
 endmodule
 
-(* abc9_box_id = (9000+DELAY) *)
+(* abc9_box *)
 module \$__ABC9_DELAY (input I, output O);
   parameter DELAY = 0;
+  specify
+    (I => O) = DELAY;
+  endspecify
 endmodule
 
 // Box to emulate async behaviour of FDC*
-(* abc9_box_id = 1000, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module \$__ABC9_ASYNC0 (input A, S, output Y);
   assign Y = S ? 1'b0 : A;
+  specify
+    (A => Y) = 0;
+    (S => Y) = 764;
+  endspecify
 endmodule
 
 // Box to emulate async behaviour of FDP*
-(* abc9_box_id = 1001, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module \$__ABC9_ASYNC1 (input A, S, output Y);
   assign Y = S ? 1'b1 : A;
+  specify
+    (A => Y) = 0;
+    (S => Y) = 764;
+  endspecify
 endmodule
 
 // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}
@@ -56,12 +75,29 @@ endmodule
 //   is only committed on the next clock edge).
 //   To model the combinatorial path, such cells have to be split
 //   into comb and seq parts, with this box modelling only the former.
-(* abc9_box_id=2000 *)
+(* abc9_box *)
 module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
+  specify
+    (S[0] => Y) = 642;
+    (S[1] => Y) = 631;
+    (S[2] => Y) = 472;
+    (S[3] => Y) = 407;
+    (S[4] => Y) = 238;
+    (S[5] => Y) = 127;
+  endspecify
 endmodule
 // Box to emulate comb/seq behaviour of RAM128
-(* abc9_box_id=2001 *)
+(* abc9_box *)
 module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
+  specify
+    (S[0] => Y) = 1028;
+    (S[1] => Y) = 1017;
+    (S[2] => Y) =  858;
+    (S[3] => Y) =  793;
+    (S[4] => Y) =  624;
+    (S[5] => Y) =  513;
+    (S[6] => Y) =  464;
+  endspecify
 endmodule
 
 // Boxes used to represent the comb behaviour of various modes
@@ -77,9 +113,43 @@ module __NAME__ (
     input [47:0] $PCOUT,
     output [47:0] P,
     output [47:0] PCOUT);
-endmodule
 """
-(* abc9_box_id=3000 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT)
-(* abc9_box_id=3001 *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT)
-(* abc9_box_id=3002 *) `ABC9_DSP48E1($__ABC9_DSP48E1)
+(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT)
+  specify
+    ($A *> P) = 2823;
+    ($B *> P) = 2690;
+    ($C *> P) = 1325;
+    ($P *> P) = 0;
+    ($A *> PCOUT) = 2970;
+    ($B *> PCOUT) = 2838;
+    ($C *> PCOUT) = 1474;
+    ($PCOUT *> PCOUT) = 0;
+  endspecify
+endmodule
+(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT)
+  specify
+    ($A *> P) = 3806;
+    ($B *> P) = 2690;
+    ($C *> P) = 1325;
+    ($D *> P) = 3700;
+    ($P *> P) = 0;
+    ($A *> PCOUT) = 3954;
+    ($B *> PCOUT) = 2838;
+    ($C *> PCOUT) = 1474;
+    ($D *> PCOUT) = 3700;
+    ($PCOUT *> PCOUT) = 0;
+  endspecify
+endmodule
+(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1)
+  specify
+    ($A *> P) = 1523;
+    ($B *> P) = 1509;
+    ($C *> P) = 1325;
+    ($P *> P) = 0;
+    ($A *> PCOUT) = 1671;
+    ($B *> PCOUT) = 1658;
+    ($C *> PCOUT) = 1474;
+    ($PCOUT *> PCOUT) = 0;
+  endspecify
+endmodule
 `undef ABC9_DSP48E1
diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
deleted file mode 100644
index 48d492801..000000000
--- a/techlibs/xilinx/abc9_xc7.box
+++ /dev/null
@@ -1,384 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
-#                 https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf
-
-# NB: Box inputs/outputs must each be in the same order
-#     as their corresponding module definition
-#     (with exceptions detailed below)
-
-# Box 1 : MUXF7
-#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
-# name ID w/b ins outs
-MUXF7  1  1   3   1
-#I0 I1  S0
-204 208 286 # O
-
-# Box 2 : MUXF8
-#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464
-# name ID w/b ins outs
-MUXF8  2  1   3   1
-#I0 I1 S0
-104 94 273 # O
-
-# Box 3 : $__MUXF78
-#         (private cell used to preserve 2xMUXF7 + 1xMUXF8
-#          an atomic unit so that ABC cannot optimise just
-#          one of the MUXF7 away and expect to save on its
-#          delay, since MUXF8 is only reachable through an
-#          MUXF7)
-# name    ID w/b ins outs
-$__MUXF78 3  1   6   1
-#I0 I1  I2  I3  S0  S1
-294 297 311 317 390 273 # O
-
-# Box 4 : CARRY4 + CARRY4_[ABCD]X
-#   (Exception: carry chain input/output must be the
-#        last input and output and the entire bus has been
-#        moved there overriding the otherwise
-#        alphabetical ordering)
-#   Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
-# name ID w/b ins outs
-CARRY4 4  1   10  8
-#CYINIT DI0 DI1 DI2 DI3 S0  S1  S2  S3  CI
-482     -   -   -   -   223 -   -   -   222 # O0
-598     407 -   -   -   400 205 -   -   334 # O1
-584     556 537 -   -   523 558 226 -   239 # O2
-642     615 596 438 -   582 618 330 227 313 # O3
-536     379 -   -   -   340 -   -   -   271 # CO0
-494     465 445 -   -   433 469 -   -   157 # CO1
-592     540 520 356 -   512 548 292 -   228 # CO2
-580     526 507 398 385 508 528 378 380 114 # CO3
-
-# Box 1000 : $__ABC9_ASYNC0
-#            (private cell to emulate async behaviour of FDC*)
-# name         ID   w/b ins outs
-$__ABC9_ASYNC0 1000 1   2   1
-#A S
-0  764 # Y
-
-# Box 1001 : $__ABC9_ASYNC1
-#            (private cell to emulate async behaviour of FDP*)
-# name         ID   w/b ins outs
-$__ABC9_ASYNC1 1001 1   2   1
-#A S
-0  764 # Y
-
-# Box 2000 : $__ABC9_LUT6
-#            (private cell to emulate async behaviour of LUTRAMs)
-# SLICEM/A6LUT
-# name       ID   w/b ins outs
-$__ABC9_LUT6 2000 0   7   1
-#A S0  S1  S2  S3  S4  S5
-0  642 631 472 407 238 127 # Y
-
-# Box 2001 : $__ABC9_LUT6
-#            (private cell to emulate async behaviour of LUTRAMs)
-# name       ID   w/b ins outs
-$__ABC9_LUT7 2001 0   8   1
-#A S0   S1   S2  S3  S4  S5  S6
-0  1047 1036 877 812 643 532 478 # Y
-
-# Box 3000 : $__ABC9_DSP48E1_MULT
-#            (private cell to emulate comb behaviour of a DSP48E1 mode)
-# name               ID   w/b ins outs
-$__ABC9_DSP48E1_MULT 3000 0   265 96
-#A0  A1   A2   A3   A4   A5   A6   A7   A8   A9   A10  A11  A12  A13  A14  A15  A16  A17  A18  A19  A20  A21  A22  A23  A24  A25  A26  A27  A28  A29  B0   B1   B2   B3   B4   B5   B6   B7   B8   B9   B10  B11  B12  B13  B14  B15  B16  B17  C0   C1   C2   C3   C4   C5   C6   C7   C8   C9   C10  C11  C12  C13  C14  C15  C16  C17  C18  C19  C20  C21  C22  C23  C24  C25  C26  C27  C28  C29  C30  C31  C32  C33  C34  C35  C36  C37  C38  C39  C40  C41  C42  C43  C44  C45  C46  C47  D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P0
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P1
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P2
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P3
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P4
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P5
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P6
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P7
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P8
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P9
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P10
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P11
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P12
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P13
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P14
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P15
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P16
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P17
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P18
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P19
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P20
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P21
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P22
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P23
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P24
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P25
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P26
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P27
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P28
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P29
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P30
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P31
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P32
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P33
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P34
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P35
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P36
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P37
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P38
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P39
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P40
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P41
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P42
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P43
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P44
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P45
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P46
-2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2823 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P47
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT0
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT1
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT2
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT3
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT4
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT5
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT6
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT7
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT8
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT9
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT10
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT11
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT12
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT13
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT14
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT15
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT16
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT17
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT18
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT19
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT20
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT21
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT22
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT23
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT24
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT25
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT26
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT27
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT28
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT29
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT30
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT31
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT32
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT33
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT34
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT35
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT36
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT37
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT38
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT39
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT40
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT41
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT42
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT43
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT44
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT45
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT46
-2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2970 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT47
-
-# Box 3001 : $__ABC9_DSP48E1_MULT_DPORT
-#            (private cell to emulate comb behaviour of a DSP48E1 mode)
-# name                     ID   w/b ins outs
-$__ABC9_DSP48E1_MULT_DPORT 3001 0   265 96
-#A0  A1   A2   A3   A4   A5   A6   A7   A8   A9   A10  A11  A12  A13  A14  A15  A16  A17  A18  A19  A20  A21  A22  A23  A24  A25  A26  A27  A28  A29  B0   B1   B2   B3   B4   B5   B6   B7   B8   B9   B10  B11  B12  B13  B14  B15  B16  B17  C0   C1   C2   C3   C4   C5   C6   C7   C8   C9   C10  C11  C12  C13  C14  C15  C16  C17  C18  C19  C20  C21  C22  C23  C24  C25  C26  C27  C28  C29  C30  C31  C32  C33  C34  C35  C36  C37  C38  C39  C40  C41  C42  C43  C44  C45  C46  C47  D0   D1   D2   D3   D4   D5   D6   D7   D8   D9   D10  D11  D12  D13  D14  D15  D16  D17  D18  D19  D20  D21  D22  D23  D24  P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P0
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P1
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P2
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P3
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P4
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P5
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P6
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P7
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P8
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P9
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P10
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P11
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P12
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P13
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P14
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P15
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P16
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P17
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P18
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P19
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P20
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P21
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P22
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P23
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P24
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P25
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P26
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P27
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P28
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P29
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P30
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P31
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P32
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P33
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P34
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P35
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P36
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P37
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P38
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P39
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P40
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P41
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P42
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P43
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P44
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P45
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P46
-3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 3806 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 2690 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P47
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT0
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT1
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT2
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT3
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT4
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT5
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT6
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT7
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT8
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT9
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT10
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT11
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT12
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT13
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT14
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT15
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT16
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT17
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT18
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT19
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT20
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT21
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT22
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT23
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT24
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT25
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT26
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT27
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT28
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT29
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT30
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT31
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT32
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT33
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT34
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT35
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT36
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT37
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT38
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT39
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT40
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT41
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT42
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT43
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT44
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT45
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT46
-3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 3954 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 2838 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 3700 0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT47
-
-# Box 3002 : $__ABC9_DSP48E1
-#            (private cell to emulate comb behaviour of a DSP48E1 mode)
-# name          ID   w/b ins outs
-$__ABC9_DSP48E1 3002 0   265 96
-#A0  A1   A2   A3   A4   A5   A6   A7   A8   A9   A10  A11  A12  A13  A14  A15  A16  A17  A18  A19  A20  A21  A22  A23  A24  A25  A26  A27  A28  A29  B0   B1   B2   B3   B4   B5   B6   B7   B8   B9   B10  B11  B12  B13  B14  B15  B16  B17  C0   C1   C2   C3   C4   C5   C6   C7   C8   C9   C10  C11  C12  C13  C14  C15  C16  C17  C18  C19  C20  C21  C22  C23  C24  C25  C26  C27  C28  C29  C30  C31  C32  C33  C34  C35  C36  C37  C38  C39  C40  C41  C42  C43  C44  C45  C46  C47  D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 PCIN0 PCIN1 PCIN2 PCIN3 PCIN4 PCIN5 PCIN6 PCIN7 PCIN8 PCIN9 PCIN10 PCIN11 PCIN12 PCIN13 PCIN14 PCIN15 PCIN16 PCIN17 PCIN18 PCIN19 PCIN20 PCIN21 PCIN22 PCIN23 PCIN24 PCIN25 PCIN26 PCIN27 PCIN28 PCIN29 PCIN30 PCIN31 PCIN32 PCIN33 PCIN34 PCIN35 PCIN36 PCIN37 PCIN38 PCIN39 PCIN40 PCIN41 PCIN42 PCIN43 PCIN44 PCIN45 PCIN46 PCIN47 PCOUT0 PCOUT1 PCOUT2 PCOUT3 PCOUT4 PCOUT5 PCOUT6 PCOUT7 PCOUT8 PCOUT9 PCOUT10 PCOUT11 PCOUT12 PCOUT13 PCOUT14 PCOUT15 PCOUT16 PCOUT17 PCOUT18 PCOUT19 PCOUT20 PCOUT21 PCOUT22 PCOUT23 PCOUT24 PCOUT25 PCOUT26 PCOUT27 PCOUT28 PCOUT29 PCOUT30 PCOUT31 PCOUT32 PCOUT33 PCOUT34 PCOUT35 PCOUT36 PCOUT37 PCOUT38 PCOUT39 PCOUT40 PCOUT41 PCOUT42 PCOUT43 PCOUT44 PCOUT45 PCOUT46 PCOUT47
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P0
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P1
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P2
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P3
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P4
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P5
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P6
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P7
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P8
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P9
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P10
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P11
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P12
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P13
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P14
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P15
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P16
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P17
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P18
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P19
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P20
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P21
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P22
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P23
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P24
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P25
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P26
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P27
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P28
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P29
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P30
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P31
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P32
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P33
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P34
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P35
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P36
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P37
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P38
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P39
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P40
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P41
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P42
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P43
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P44
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P45
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P46
-1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1523 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1509 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 1325 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1107  1107  1107  1107  1107  1107  1107  1107  1107  1107  1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   1107   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # P47
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT0
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT1
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT2
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT3
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT4
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT5
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT6
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT7
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT8
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT9
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT10
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT11
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT12
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT13
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT14
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT15
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT16
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT17
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT18
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT19
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT20
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT21
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT22
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT23
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT24
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT25
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT26
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT27
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT28
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT29
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT30
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT31
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT32
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT33
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT34
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT35
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT36
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT37
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT38
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT39
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT40
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT41
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT42
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT43
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT44
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT45
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT46
-1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1671 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1658 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 1474 -  -  -  -  -  -  -  -  -  -  -   -   -   -   -   -   -   -   -   -   -   -   -   -   -   0  0  0  0  0  0  0  0  0  0  0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   1255  1255  1255  1255  1255  1255  1255  1255  1255  1255  1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   1255   0      0      0      0      0      0      0      0      0      0      0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0       0      # PCOUT47
diff --git a/techlibs/xilinx/abc9_xc7.lut b/techlibs/xilinx/abc9_xc7.lut
deleted file mode 100644
index bcbdec127..000000000
--- a/techlibs/xilinx/abc9_xc7.lut
+++ /dev/null
@@ -1,15 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf
-#            and  https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json
-
-# K	area	delay
-1 	1	127
-2	2	127 238
-3	3	127 238 407
-4	3	127 238 407 472
-5	3	127 238 407 472 631
-6	5	127 238 407 472 631 642
-		# (F7[AB]MUX.S + [AC]OUTMUX) / 2
-7	10	464 513 624 793 858 1017 1028
-		# F8MUX.S+BOUTMUX
-		    # F8MUX.I0+F7MUX.S+BOUTMUX
-8	20	468 585 634 745 914 979 1138 1149
diff --git a/techlibs/xilinx/abc9_xc7_nowide.lut b/techlibs/xilinx/abc9_xc7_nowide.lut
deleted file mode 100644
index fab48c879..000000000
--- a/techlibs/xilinx/abc9_xc7_nowide.lut
+++ /dev/null
@@ -1,10 +0,0 @@
-# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf
-#            and  https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json
-
-# K	area	delay
-1 	1	127
-2	2	127 238
-3	3	127 238 407
-4	3	127 238 407 472
-5	3	127 238 407 472 631
-6	5	127 238 407 472 631 642
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index a1fe56fa1..1318389f0 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -318,14 +318,26 @@ module MUXF6(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
 endmodule
 
-(* abc9_box_id = 1, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
+    (I0 => O) = 204;
+    (I1 => O) = 208;
+    (S => O) = 286;
+  endspecify
 endmodule
 
-(* abc9_box_id = 2, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module MUXF8(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
+  specify
+    // Max delays from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L462-L464
+    (I0 => O) = 104;
+    (I1 => O) = 94;
+    (S => O) = 273;
+  endspecify
 endmodule
 
 module MUXF9(output O, input I0, I1, S);
@@ -336,7 +348,7 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc9_box_id = 4, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module CARRY4(
   (* abc9_carry *)
   output [3:0] CO,
@@ -351,6 +363,61 @@ module CARRY4(
   assign CO[1] = S[1] ? CO[0] : DI[1];
   assign CO[2] = S[2] ? CO[1] : DI[2];
   assign CO[3] = S[3] ? CO[2] : DI[3];
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L11-L46
+    (CYINIT => O[0]) = 482;
+    (S[0]   => O[0]) = 223;
+    (CI     => O[0]) = 222;
+    (CYINIT => O[1]) = 598;
+    (DI[0]  => O[1]) = 407;
+    (S[0]   => O[1]) = 400;
+    (S[1]   => O[1]) = 205;
+    (CI     => O[1]) = 334;
+    (CYINIT => O[2]) = 584;
+    (DI[0]  => O[2]) = 556;
+    (DI[1]  => O[2]) = 537;
+    (S[0]   => O[2]) = 523;
+    (S[1]   => O[2]) = 558;
+    (S[2]   => O[2]) = 226;
+    (CI     => O[2]) = 239;
+    (CYINIT => O[3]) = 642;
+    (DI[0]  => O[3]) = 615;
+    (DI[1]  => O[3]) = 596;
+    (DI[2]  => O[3]) = 438;
+    (S[0]   => O[3]) = 582;
+    (S[1]   => O[3]) = 618;
+    (S[2]   => O[3]) = 330;
+    (S[3]   => O[3]) = 227;
+    (CI     => O[3]) = 313;
+    (CYINIT => CO[0]) = 536;
+    (DI[0]  => CO[0]) = 379;
+    (S[0]   => CO[0]) = 340;
+    (CI     => CO[0]) = 271;
+    (CYINIT => CO[1]) = 494;
+    (DI[0]  => CO[1]) = 465;
+    (DI[1]  => CO[1]) = 445;
+    (S[0]   => CO[1]) = 433;
+    (S[1]   => CO[1]) = 469;
+    (CI     => CO[1]) = 157;
+    (CYINIT => CO[2]) = 592;
+    (DI[0]  => CO[2]) = 540;
+    (DI[1]  => CO[2]) = 520;
+    (DI[2]  => CO[2]) = 356;
+    (S[0]   => CO[2]) = 512;
+    (S[1]   => CO[2]) = 548;
+    (S[2]   => CO[2]) = 292;
+    (CI     => CO[2]) = 228;
+    (CYINIT => CO[3]) = 580;
+    (DI[0]  => CO[3]) = 526;
+    (DI[1]  => CO[3]) = 507;
+    (DI[2]  => CO[3]) = 398;
+    (DI[3]  => CO[3]) = 385;
+    (S[0]   => CO[3]) = 508;
+    (S[1]   => CO[3]) = 528;
+    (S[2]   => CO[3]) = 378;
+    (S[3]   => CO[3]) = 380;
+    (CI     => CO[3]) = 114;
+  endspecify
 endmodule
 
 module CARRY8(
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index db39330ae..4011e09b0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,7 +619,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (dff_mode)
 					techmap_args += " -D DFF_MODE";
 				run("techmap " + techmap_args);
-				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
+				run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v");
 				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
 				if (active_design->scratchpad.count(k))

From 577545488a81e1f9b84b214d6d02187aac28af6c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 11 Feb 2020 14:22:43 -0800
Subject: [PATCH 05/46] xilinx: use specify blocks in place of
 abc9_{arrival,required}

---
 README.md                   |  15 +-
 passes/techmap/abc9_ops.cc  | 422 ++++++++++++++++----------
 techlibs/xilinx/cells_sim.v | 580 +++++++++++++++++++++++++-----------
 3 files changed, 670 insertions(+), 347 deletions(-)

diff --git a/README.md b/README.md
index 9c15fe3d9..8cd347497 100644
--- a/README.md
+++ b/README.md
@@ -364,25 +364,14 @@ Verilog Attributes and non-standard features
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 
-- The module attribute ``abc9_box_id`` specifies a positive integer linking a
-  blackbox or whitebox definition to a corresponding entry in a `abc9`
-  box-file.
+- The module attribute ``abc9_box`` is a boolean specifying a blackbox or
+  whitebox definition for use by `abc9`.
 
 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
   carry-out (if output port) ports of a box. This information is necessary for
   `abc9` to preserve the integrity of carry-chains. Specifying this attribute
   onto a bus port will affect only its most significant bit.
 
-- The output port attribute ``abc9_arrival`` specifies an integer, or a string
-  of space-separated integers to be used as the arrival time of this blackbox
-  port. It can be used, for example, to specify the clk-to-Q delay of a flip-
-  flop output for consideration during `abc9` techmapping.
-
-- The input port attribute ``abc9_required`` specifies an integer, or a string
-  of space-separated integers to be used as the required time of this blackbox
-  port. It can be used, for example, to specify the setup-time of a flip-flop
-  input for consideration during `abc9` techmapping.
-
 - The module attribute ``abc9_flop`` is a boolean marking the module as a
   flip-flop. This allows `abc9` to analyse its contents in order to perform
   sequential synthesis.
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index bbbbc45d0..9abe6af9f 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -70,54 +70,6 @@ void check(RTLIL::Design *design)
 					carry_out = port_name;
 				}
 			}
-
-			auto it = w->attributes.find("\\abc9_arrival");
-			if (it != w->attributes.end()) {
-				int count = 0;
-				if (it->second.flags == 0) {
-					if (it->second.as_int() < 0)
-						log_error("%s.%s has negative arrival value %d!\n", log_id(m), log_id(port_name),
-								it->second.as_int());
-					count++;
-				}
-				else
-					for (const auto &tok : split_tokens(it->second.decode_string())) {
-						if (tok.find_first_not_of("0123456789") != std::string::npos)
-							log_error("%s.%s has non-integer arrival value '%s'!\n", log_id(m), log_id(port_name),
-									tok.c_str());
-						if (atoi(tok.c_str()) < 0)
-							log_error("%s.%s has negative arrival value %s!\n", log_id(m), log_id(port_name),
-									tok.c_str());
-						count++;
-					}
-				if (count > 1 && count != GetSize(w))
-					log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(m), log_id(port_name),
-							GetSize(w), log_signal(it->second), count);
-			}
-
-			it = w->attributes.find("\\abc9_required");
-			if (it != w->attributes.end()) {
-				int count = 0;
-				if (it->second.flags == 0) {
-					if (it->second.as_int() < 0)
-						log_error("%s.%s has negative required value %d!\n", log_id(m), log_id(port_name),
-								it->second.as_int());
-					count++;
-				}
-				else
-					for (const auto &tok : split_tokens(it->second.decode_string())) {
-						if (tok.find_first_not_of("0123456789") != std::string::npos)
-							log_error("%s.%s has non-integer required value '%s'!\n", log_id(m), log_id(port_name),
-									tok.c_str());
-						if (atoi(tok.c_str()) < 0)
-							log_error("%s.%s has negative required value %s!\n", log_id(m), log_id(port_name),
-									tok.c_str());
-						count++;
-					}
-				if (count > 1 && count != GetSize(w))
-					log_error("%s.%s is %d bits wide but abc9_required = %s has %d value(s)!\n", log_id(m), log_id(port_name),
-							GetSize(w), log_signal(it->second), count);
-			}
 		}
 
 		if (carry_in != IdString() && carry_out == IdString())
@@ -428,16 +380,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design)
 {
-	pool<Module*> flops;
+	// Derive and collect all blackbox modules, and collect all blackbox instantiations
+	pool<Module*> derived;
 	std::vector<Cell*> cells;
-	dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
 	for (auto module : design->selected_modules()) {
 		if (module->processes.size() > 0) {
 			log("Skipping module %s as it contains processes.\n", log_id(module));
 			continue;
 		}
 
-		cells.clear();
 		for (auto cell : module->cells()) {
 			if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
 				continue;
@@ -447,119 +398,186 @@ void prep_delays(RTLIL::Design *design)
 				continue;
 			if (!inst_module->get_blackbox_attribute())
 				continue;
-			if (inst_module->get_bool_attribute(ID(abc9_flop))) {
-				IdString derived_type = inst_module->derive(design, cell->parameters);
-				inst_module = design->module(derived_type);
-				log_assert(inst_module);
-				flops.insert(inst_module);
-				continue; // because all flop required times
-				          //   will be captured in the flop box
-			}
 			if (inst_module->attributes.count(ID(abc9_box)))
 				continue;
+			IdString derived_type = inst_module->derive(design, cell->parameters);
+			inst_module = design->module(derived_type);
+			log_assert(inst_module);
+			derived.insert(inst_module);
+
 			cells.emplace_back(cell);
 		}
+	}
 
-		for (auto cell : cells) {
-			RTLIL::Module* inst_module = module->design->module(cell->type);
-			log_assert(inst_module);
-			auto &cell_requireds = requireds_cache[cell->type];
-			for (auto &conn : cell->connections_) {
-				auto port_wire = inst_module->wire(conn.first);
-				if (!port_wire->port_input)
+	// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
+	std::vector<Module*> flops;
+	dict<SigBit, int> arrivals, requireds;
+	pool<Wire*> ports;
+	std::stringstream ss;
+	for (auto module : derived) {
+		if (module->get_bool_attribute(ID(abc9_flop)))
+			flops.push_back(module);
+
+		arrivals.clear();
+		requireds.clear();
+		for (auto cell : module->cells()) {
+			if (cell->type == ID($specify3)) {
+				auto src = cell->getPort(ID(SRC));
+				auto dat = cell->getPort(ID(DAT));
+				auto dst = cell->getPort(ID(DST));
+				for (const auto &c : src.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+				for (const auto &c : dat.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where DAT '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dat));
+				for (const auto &c : dst.chunks())
+					if (!c.wire->port_output)
+						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
+				if (!cell->getParam(ID(EDGE_EN)).as_bool())
 					continue;
+				int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
+				int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+				int max = std::max(rise_max,fall_max);
+				if (max < 0) {
+					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+					continue;
+				}
+				for (auto d : dst)
+					arrivals[d] = std::max(arrivals[d], max);
+			}
+			else if (cell->type == ID($specrule)) {
+				auto type = cell->getParam(ID(TYPE)).decode_string();
+				if (type != "$setup" && type != "$setuphold")
+					continue;
+				auto src = cell->getPort(ID(SRC));
+				auto dst = cell->getPort(ID(DST));
+				for (const auto &c : src.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+				for (const auto &c : dst.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
+				int setup = cell->getParam(ID(T_LIMIT)).as_int();
+				if (setup < 0) {
+					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+					continue;
+				}
+				for (const auto &s : src)
+					requireds[s] = std::max(requireds[s], setup);
+			}
+		}
 
-				auto r = cell_requireds.insert(conn.first);
-				auto &requireds = r.first->second;
-				if (r.second) {
-					auto it = port_wire->attributes.find("\\abc9_required");
-					if (it == port_wire->attributes.end())
-						continue;
-					if (it->second.flags == 0) {
-						int delay = it->second.as_int();
-						requireds.emplace_back(delay);
-					}
+		if (arrivals.empty() && requireds.empty())
+			continue;
+
+		ports.clear();
+		for (const auto &i : arrivals)
+			ports.insert(i.first.wire);
+		for (auto wire : ports) {
+			log_assert(wire->port_output);
+			ss.str("");
+			if (GetSize(wire) == 1)
+				wire->attributes[ID(abc9_arrival)] = arrivals.at(SigBit(wire,0));
+			else {
+				bool first = true;
+				for (auto b : SigSpec(wire)) {
+					if (first)
+						first = false;
 					else
-						for (const auto &tok : split_tokens(it->second.decode_string())) {
-							int delay = atoi(tok.c_str());
-							requireds.push_back(delay);
-						}
+						ss << " ";
+					auto it = arrivals.find(b);
+					if (it == arrivals.end())
+						ss << "0";
+					else
+						ss << it->second;
 				}
+				wire->attributes[ID(abc9_arrival)] = ss.str();
+			}
+		}
 
-				if (requireds.empty())
-					continue;
-
-				SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
-				auto it = requireds.begin();
-				for (int i = 0; i < GetSize(conn.second); ++i) {
-#ifndef NDEBUG
-					if (ys_debug(1)) {
-						static std::set<std::pair<IdString,IdString>> seen;
-						if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
-					}
-#endif
-					auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
-					box->setPort(ID(I), conn.second[i]);
-					box->setPort(ID(O), O[i]);
-					box->setParam(ID(DELAY), *it);
-					if (requireds.size() > 1)
-						it++;
-					conn.second[i] = O[i];
+		ports.clear();
+		for (const auto &i : requireds)
+			ports.insert(i.first.wire);
+		for (auto wire : ports) {
+			log_assert(wire->port_input);
+			ss.str("");
+			if (GetSize(wire) == 1)
+				wire->attributes[ID(abc9_required)] = requireds.at(SigBit(wire,0));
+			else {
+				bool first = true;
+				for (auto b : SigSpec(wire)) {
+					if (first)
+						first = false;
+					else
+						ss << " ";
+					auto it = requireds.find(b);
+					if (it == requireds.end())
+						ss << "0";
+					else
+						ss << it->second;
 				}
+				wire->attributes[ID(abc9_required)] = ss.str();
 			}
 		}
 	}
 
-	int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
-	std::stringstream ss;
-	for (auto flop_module : flops) {
-		int num_inputs = 0, num_outputs = 0;
-		for (auto port_name : flop_module->ports) {
-			auto wire = flop_module->wire(port_name);
-			log_assert(GetSize(wire) == 1);
-			if (wire->port_input) num_inputs++;
-			if (wire->port_output) num_outputs++;
-		}
-		log_assert(num_outputs == 1);
+	// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
+	//   with (* abc9_required *) attributes
+	dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
+	for (auto cell : cells) {
+		auto module = cell->module;
+		RTLIL::Module* inst_module = module->design->module(cell->type);
+		log_assert(inst_module);
+		IdString derived_type = inst_module->derive(design, cell->parameters);
+		inst_module = design->module(derived_type);
+		log_assert(inst_module);
 
-		auto r = flop_module->attributes.insert(ID(abc9_box_id));
-		if (r.second)
-			r.first->second = ++abc9_box_id;
-
-		ss << log_id(flop_module) << " " << r.first->second.as_int();
-		ss << " " << (flop_module->get_bool_attribute(ID::whitebox) ? "1" : "0");
-		ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
-
-		ss << "#";
-		bool first = true;
-		for (auto port_name : flop_module->ports) {
-			auto wire = flop_module->wire(port_name);
-			if (!wire->port_input)
+		auto &cell_requireds = requireds_cache[cell->type];
+		for (auto &conn : cell->connections_) {
+			auto port_wire = inst_module->wire(conn.first);
+			if (!port_wire->port_input)
 				continue;
-			if (first)
-				first = false;
-			else
-				ss << " ";
-			ss << log_id(wire);
-		}
-		ss << " abc9_ff.Q" << std::endl;
 
-		first = true;
-		for (auto port_name : flop_module->ports) {
-			auto wire = flop_module->wire(port_name);
-			if (!wire->port_input)
+			auto r = cell_requireds.insert(conn.first);
+			auto &requireds = r.first->second;
+			if (r.second) {
+				auto it = port_wire->attributes.find("\\abc9_required");
+				if (it == port_wire->attributes.end())
+					continue;
+				if (it->second.flags == 0) {
+					int delay = it->second.as_int();
+					requireds.emplace_back(delay);
+				}
+				else
+					for (const auto &tok : split_tokens(it->second.decode_string())) {
+						int delay = atoi(tok.c_str());
+						requireds.push_back(delay);
+					}
+			}
+
+			if (requireds.empty())
 				continue;
-			if (first)
-				first = false;
-			else
-				ss << " ";
-			ss << wire->attributes.at("\\abc9_required", 0).as_int();
+
+			SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+			auto it = requireds.begin();
+			for (int i = 0; i < GetSize(conn.second); ++i) {
+#ifndef NDEBUG
+				if (ys_debug(1)) {
+					static std::set<std::pair<IdString,IdString>> seen;
+					if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
+				}
+#endif
+				auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+				box->setPort(ID(I), conn.second[i]);
+				box->setPort(ID(O), O[i]);
+				box->setParam(ID(DELAY), *it);
+				if (requireds.size() > 1)
+					it++;
+				conn.second[i] = O[i];
+			}
 		}
-		// Last input is 'abc9_ff.Q'
-		ss << " 0" << std::endl << std::endl;
 	}
-	design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
-	design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
 }
 
 void prep_lut(RTLIL::Design *design, int maxlut)
@@ -587,7 +605,10 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 				log_assert(o == d);
 			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
 			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
-			specify.push_back(std::max(rise_max,fall_max));
+			int max = std::max(rise_max,fall_max);
+			if (max < 0)
+				log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
+			specify.push_back(max);
 		}
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
@@ -618,10 +639,57 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 void prep_box(RTLIL::Design *design)
 {
 	std::stringstream ss;
-	ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
-
-	int abc9_box_id = design->scratchpad_get_int("abc9_ops.box_id");
+	int abc9_box_id = 1;
+	dict<IdString,std::vector<IdString>> box_ports;
 	for (auto module : design->modules()) {
+		if (module->get_bool_attribute(ID(abc9_flop))) {
+			int num_inputs = 0, num_outputs = 0;
+			for (auto port_name : module->ports) {
+				auto wire = module->wire(port_name);
+				log_assert(GetSize(wire) == 1);
+				if (wire->port_input) num_inputs++;
+				if (wire->port_output) num_outputs++;
+			}
+			log_assert(num_outputs == 1);
+
+			auto r = module->attributes.insert(ID(abc9_box_id));
+			if (r.second)
+				r.first->second = abc9_box_id++;
+
+			ss << log_id(module) << " " << r.first->second.as_int();
+			ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+			ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+
+			ss << "#";
+			bool first = true;
+			for (auto port_name : module->ports) {
+				auto wire = module->wire(port_name);
+				if (!wire->port_input)
+					continue;
+				if (first)
+					first = false;
+				else
+					ss << " ";
+				ss << log_id(wire);
+			}
+			ss << " abc9_ff.Q" << std::endl;
+
+			first = true;
+			for (auto port_name : module->ports) {
+				auto wire = module->wire(port_name);
+				if (!wire->port_input)
+					continue;
+				if (first)
+					first = false;
+				else
+					ss << " ";
+				ss << wire->attributes.at("\\abc9_required", 0).as_int();
+			}
+			// Last input is 'abc9_ff.Q'
+			ss << " 0" << std::endl << std::endl;
+			continue;
+		}
+
 		auto it = module->attributes.find(ID(abc9_box));
 		if (it == module->attributes.end())
 			continue;
@@ -631,7 +699,33 @@ void prep_box(RTLIL::Design *design)
 		dict<std::pair<SigBit,SigBit>, std::string> table;
 		std::vector<SigBit> inputs;
 		std::vector<SigBit> outputs;
-		for (auto port_name : module->ports) {
+
+		auto r = box_ports.insert(module->name);
+		if (r.second) {
+			// Make carry in the last PI, and carry out the last PO
+			//   since ABC requires it this way
+			IdString carry_in, carry_out;
+			for (const auto &port_name : module->ports) {
+				auto w = module->wire(port_name);
+				log_assert(w);
+				if (w->get_bool_attribute("\\abc9_carry")) {
+					log_assert(w->port_input != w->port_output);
+					if (w->port_input)
+						carry_in = port_name;
+					else if (w->port_output)
+						carry_out = port_name;
+				}
+				else
+					r.first->second.push_back(port_name);
+			}
+
+			if (carry_in != IdString()) {
+				r.first->second.push_back(carry_in);
+				r.first->second.push_back(carry_out);
+			}
+		}
+
+		for (auto port_name : r.first->second) {
 			auto wire = module->wire(port_name);
 			if (wire->port_input)
 				for (int i = 0; i < GetSize(wire); i++)
@@ -654,17 +748,29 @@ void prep_box(RTLIL::Design *design)
 			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
 			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
 			int max = std::max(rise_max,fall_max);
-			for (auto s : src)
-				for (auto d : dst) {
-					auto r = table.insert(std::make_pair(s,d));
+			if (max < 0)
+				log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
+			if (cell->getParam(ID(FULL)).as_bool()) {
+				for (auto s : src)
+					for (auto d : dst) {
+						auto r = table.insert(std::make_pair(s,d));
+						log_assert(r.second);
+						r.first->second = std::to_string(max);
+					}
+			}
+			else {
+				log_assert(GetSize(src) == GetSize(dst));
+				for (auto i = 0; i < GetSize(src); i++) {
+					auto r = table.insert(std::make_pair(src[i],dst[i]));
 					log_assert(r.second);
 					r.first->second = std::to_string(max);
 				}
+			}
 		}
-		auto r = module->attributes.insert(ID(abc9_box_id));
-		log_assert(r.second);
-		r.first->second = ++abc9_box_id;
+		auto r2 = module->attributes.insert(ID(abc9_box_id));
+		log_assert(r2.second);
 		ss << log_id(module) << " " << abc9_box_id;
+		r2.first->second = abc9_box_id++;
 		ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
 		ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
 		bool first = true;
@@ -700,17 +806,17 @@ void prep_box(RTLIL::Design *design)
 		ss << std::endl;
 	}
 
+	// ABC expects at least one box
+	if (ss.tellp() == 0)
+		ss << "(dummy) 1 0 0 0";
+
 	design->scratchpad_set_string("abc9_ops.box_library", ss.str());
-	design->scratchpad_set_int("abc9_ops.box_id", abc9_box_id);
 }
 
 void write_box(RTLIL::Module *module, const std::string &dst) {
 	std::ofstream ofs(dst);
 	log_assert(ofs.is_open());
 	ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
-	// ABC expects at least one box
-	if (ofs.tellp() == 0)
-		ofs << "(dummy) 1 0 0 0";
 	ofs.close();
 }
 
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1318389f0..f9d837e4c 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -477,18 +477,14 @@ endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDRE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
   (* invertible_pin = "IS_R_INVERTED" *)
-  (* abc9_required=404 *)
   input R
 );
   parameter [0:0] INIT = 1'b0;
@@ -496,44 +492,58 @@ module FDRE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
+  generate
+  case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //$setup(D , posedge C, -46); // Negative times not currently supported
+      $setup(CE, posedge C, 109);
+      $setup(R , posedge C, 404);
+    endspecify
+  else
+    specify
+      if (CE) (negedge C => (Q : D)) = 303;
+      //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+      $setup(CE, negedge C, 109);
+      $setup(R , negedge C, 404);
+    endspecify
+  endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDRE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
-  (* abc9_required=404 *)
   input R
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    $setup(CE, negedge C, 109);
+    $setup(R , negedge C, 404);
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDSE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
   (* invertible_pin = "IS_S_INVERTED" *)
-  (* abc9_required=404 *)
   input S
 );
   parameter [0:0] INIT = 1'b1;
@@ -541,28 +551,46 @@ module FDSE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
+  generate
+  case (|IS_C_INVERTED)
     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
+      $setup(CE, posedge C, 109);
+      $setup(S , posedge C, 404);
+    endspecify
+  else
+    specify
+        if (CE) (negedge C => (Q : D)) = 303;
+        //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+        $setup(CE, negedge C, 109);
+        $setup(S , negedge C, 404);
+    endspecify
+  endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDSE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
-  (* abc9_required=404 *)
   input S
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    $setup(CE, negedge C, 109);
+    $setup(S , negedge C, 404);
+  endspecify
 endmodule
 
 module FDRSE (
@@ -571,7 +599,6 @@ module FDRSE (
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
   (* invertible_pin = "IS_CE_INVERTED" *)
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
   input D,
@@ -603,18 +630,14 @@ endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDCE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_CLR_INVERTED" *)
-  (* abc9_required=764 *)
   input CLR,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D
 );
   parameter [0:0] INIT = 1'b0;
@@ -622,46 +645,60 @@ module FDCE (
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
+  generate
+  case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
     2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
+      $setup(CE , posedge C, 109);
+      $setup(CLR, posedge C, 764);
+    endspecify
+  else
+    specify
+        if (CE) (negedge C => (Q : D)) = 303;
+        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+        $setup(CE , negedge C, 109);
+        $setup(CLR, negedge C, 764);
+    endspecify
+ endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDCE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  (* abc9_required=764 *)
   input CLR,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D
 );
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    $setup(CE , negedge C, 109);
+    $setup(CLR, negedge C, 764);
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDPE (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
-  (* abc9_required=109 *)
   input CE,
   (* invertible_pin = "IS_D_INVERTED" *)
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
   (* invertible_pin = "IS_PRE_INVERTED" *)
-  (* abc9_required=764 *)
   input PRE
 );
   parameter [0:0] INIT = 1'b1;
@@ -674,25 +711,42 @@ module FDPE (
     2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  endcase
+  if (!IS_C_INVERTED)
+    specify
+      if (CE) (posedge C => (Q : D)) = 303;
+      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
+      $setup(CE , posedge C, 109);
+      $setup(PRE, posedge C, 764);
+    endspecify
+  else
+    specify
+        if (CE) (negedge C => (Q : D)) = 303;
+        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+        $setup(CE , negedge C, 109);
+        $setup(PRE, negedge C, 764);
+    endspecify
+  endgenerate
 endmodule
 
 (* abc9_flop, lib_whitebox *)
 module FDPE_1 (
-  (* abc9_arrival=303 *)
   output reg Q,
   (* clkbuf_sink *)
   input C,
-  (* abc9_required=109 *)
   input CE,
-  //(* abc9_required=-46 *) // Negative required times not currently supported
   input D,
-  (* abc9_required=764 *)
   input PRE
 );
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+  specify
+    if (CE) (negedge C => (Q : D)) = 303;
+    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    $setup(CE , negedge C, 109);
+    $setup(PRE, negedge C, 764);
+  endspecify
 endmodule
 
 module FDCPE (
@@ -1303,33 +1357,13 @@ module RAM16X1D_1 (
 endmodule
 
 module RAM32X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-  (* abc9_required=245 *)
-  input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
-  (* abc9_required=208 *)
-  input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-  (* abc9_required=147 *)
-  input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-  (* abc9_required=68 *)
-  input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-  (* abc9_required=66 *)
-  input  A4,
+  input  A0, A1, A2, A3, A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
   parameter INIT = 32'h0;
@@ -1341,35 +1375,61 @@ module RAM32X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (posedge WCLK => (SPO : D)) = 1153;
+        if (WE) (posedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , posedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+        $setup(A0, posedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+        $setup(A1, posedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+        $setup(A2, posedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+        $setup(A3, posedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+        $setup(A4, posedge WCLK, 66);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (negedge WCLK => (SPO : D)) = 1153;
+        if (WE) (negedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , negedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+        $setup(A0, negedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+        $setup(A1, negedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+        $setup(A2, negedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+        $setup(A3, negedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+        $setup(A4, negedge WCLK, 66);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM32X1D_1 (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-  (* abc9_required=245 *)
   input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/clBLM_R.sdf#L798
-  (* abc9_required=208 *)
   input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-  (* abc9_required=147 *)
   input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-  (* abc9_required=68 *)
   input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-  (* abc9_required=66 *)
   input  A4,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
 );
@@ -1382,39 +1442,35 @@ module RAM32X1D_1 (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => (SPO : D)) = 1153;
+    if (WE) (negedge WCLK => (DPO : D)) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , negedge WCLK, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, negedge WCLK, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+    $setup(A0, negedge WCLK, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+    $setup(A1, negedge WCLK, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+    $setup(A2, negedge WCLK, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+    $setup(A3, negedge WCLK, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+    $setup(A4, negedge WCLK, 66);
+  endspecify
 endmodule
 
 module RAM64X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-  (* abc9_required=362 *)
-  input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-  (* abc9_required=245 *)
-  input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-  (* abc9_required=208 *)
-  input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-  (* abc9_required=147 *)
-  input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-  (* abc9_required=68 *)
-  input  A4,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-  (* abc9_required=66 *)
-  input  A5,
+  input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
@@ -1426,39 +1482,62 @@ module RAM64X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (posedge WCLK => (SPO : D)) = 1153;
+        if (WE) (posedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , posedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+        $setup(A0, posedge WCLK, 362);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+        $setup(A1, posedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+        $setup(A2, posedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+        $setup(A3, posedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+        $setup(A4, posedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+        $setup(A5, posedge WCLK, 66);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        if (WE) (negedge WCLK => (SPO : D)) = 1153;
+        if (WE) (negedge WCLK => (DPO : D)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , negedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+        $setup(A0, negedge WCLK, 362);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+        $setup(A1, negedge WCLK, 245);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+        $setup(A2, negedge WCLK, 208);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+        $setup(A3, negedge WCLK, 147);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+        $setup(A4, negedge WCLK, 68);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+        $setup(A5, negedge WCLK, 66);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM64X1D_1 (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  (* abc9_arrival=1153 *)
   output DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input  D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input  WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input  WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-  (* abc9_required=362 *)
-  input  A0,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-  (* abc9_required=245 *)
-  input  A1,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-  (* abc9_required=208 *)
-  input  A2,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-  (* abc9_required=147 *)
-  input  A3,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-  (* abc9_required=68 *)
-  input  A4,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-  (* abc9_required=66 *)
-  input  A5,
+  input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
 );
   parameter INIT = 64'h0;
@@ -1470,21 +1549,35 @@ module RAM64X1D_1 (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => (SPO : D)) = 1153;
+    if (WE) (negedge WCLK => (DPO : D)) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , negedge WCLK, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, negedge WCLK, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+    $setup(A0, negedge WCLK, 362);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+    $setup(A1, negedge WCLK, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+    $setup(A2, negedge WCLK, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+    $setup(A3, negedge WCLK, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+    $setup(A4, negedge WCLK, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+    $setup(A5, negedge WCLK, 66);
+  endspecify
 endmodule
 
 module RAM128X1D (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-  //   plus 208ps to cross MUXF7
-  (* abc9_arrival=1359 *)
   output       DPO, SPO,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-  (* abc9_required=453 *)
   input        D,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input        WE,
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
   (* abc9_required="616 362 245 208 147 68 66" *)
@@ -1498,6 +1591,46 @@ module RAM128X1D (
   assign DPO = mem[DPRA];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        //   plus 208ps to cross MUXF7
+        if (WE) (posedge WCLK => (SPO : D)) = 1359;
+        if (WE) (posedge WCLK => (DPO : D)) = 1359;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , posedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
+        $setup(A[0], posedge WCLK, 616);
+        $setup(A[1], posedge WCLK, 362);
+        $setup(A[2], posedge WCLK, 245);
+        $setup(A[3], posedge WCLK, 208);
+        $setup(A[4], posedge WCLK, 147);
+        $setup(A[5], posedge WCLK, 68);
+        $setup(A[6], posedge WCLK, 66);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+        //   plus 208ps to cross MUXF7
+        if (WE) (negedge WCLK => (SPO : D)) = 1359;
+        if (WE) (negedge WCLK => (DPO : D)) = 1359;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(D , negedge WCLK, 453);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
+        $setup(A[0], negedge WCLK, 616);
+        $setup(A[1], negedge WCLK, 362);
+        $setup(A[2], negedge WCLK, 245);
+        $setup(A[3], negedge WCLK, 208);
+        $setup(A[4], negedge WCLK, 147);
+        $setup(A[5], negedge WCLK, 68);
+        $setup(A[6], negedge WCLK, 66);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM256X1D (
@@ -1521,43 +1654,19 @@ endmodule
 // Multi port.
 
 module RAM32M (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-  (* abc9_arrival="1153 1188" *)
   output [1:0] DOA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-  (* abc9_arrival="1161 1187" *)
   output [1:0] DOB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-  (* abc9_arrival="1158 1180" *)
   output [1:0] DOC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-  (* abc9_arrival="1163 1190" *)
   output [1:0] DOD,
   input  [4:0] ADDRA, ADDRB, ADDRC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792-L802
-  (* abc9_required="245 208 147 68 66" *)
   input  [4:0] ADDRD,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-  (* abc9_required="453 384" *)
   input  [1:0] DIA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-  (* abc9_required="461 354" *)
   input  [1:0] DIB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-  (* abc9_required="457 375" *)
   input  [1:0] DIC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-  (* abc9_required="310 334" *)
   input  [1:0] DID,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input        WE
 );
   parameter [63:0] INIT_A = 64'h0000000000000000;
@@ -1581,6 +1690,87 @@ module RAM32M (
       mem_c[2*ADDRD+:2] <= DIC;
       mem_d[2*ADDRD+:2] <= DID;
     end
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+        if (WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+        if (WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+        if (WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+        if (WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(ADDRD[0], posedge WCLK, 245);
+        $setup(ADDRD[1], posedge WCLK, 208);
+        $setup(ADDRD[2], posedge WCLK, 147);
+        $setup(ADDRD[3], posedge WCLK, 68);
+        $setup(ADDRD[4], posedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA[0], posedge WCLK, 453);
+        $setup(DIA[1], posedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB[0], posedge WCLK, 461);
+        $setup(DIB[1], posedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC[0], posedge WCLK, 457);
+        $setup(DIC[1], posedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID[0], posedge WCLK, 310);
+        $setup(DID[1], posedge WCLK, 334);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+        if (WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+        if (WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+        if (WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+        if (WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+        $setup(ADDRD[0], negedge WCLK, 245);
+        $setup(ADDRD[1], negedge WCLK, 208);
+        $setup(ADDRD[2], negedge WCLK, 147);
+        $setup(ADDRD[3], negedge WCLK, 68);
+        $setup(ADDRD[4], negedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA[0], negedge WCLK, 453);
+        $setup(DIA[1], negedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB[0], negedge WCLK, 461);
+        $setup(DIB[1], negedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC[0], negedge WCLK, 457);
+        $setup(DIC[1], negedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID[0], negedge WCLK, 310);
+        $setup(DID[1], negedge WCLK, 334);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+      endspecify
+  endgenerate
+
 endmodule
 
 module RAM32M16 (
@@ -1653,39 +1843,19 @@ module RAM32M16 (
 endmodule
 
 module RAM64M (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-  (* abc9_arrival=1153 *)
   output       DOA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc9_arrival=1161 *)
   output       DOB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-  (* abc9_arrival=1158 *)
   output       DOC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-  (* abc9_arrival=1163 *)
   output       DOD,
   input  [5:0] ADDRA, ADDRB, ADDRC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-  (* abc9_required="362 245 208 147 68 66" *)
   input  [5:0] ADDRD,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-  (* abc9_required=384 *)
   input        DIA,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-  (* abc9_required=354 *)
   input        DIB,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-  (* abc9_required=375 *)
   input        DIC,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-  (* abc9_required=310 *)
   input        DID,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-  (* abc9_required=654 *)
   input        WE
 );
   parameter [63:0] INIT_A = 64'h0000000000000000;
@@ -1709,6 +1879,64 @@ module RAM64M (
       mem_c[ADDRD] <= DIC;
       mem_d[ADDRD] <= DID;
     end
+  generate
+    if (!IS_WCLK_INVERTED)
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (posedge WCLK => (DOA : DIA)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (posedge WCLK => (DOB : DIB)) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (posedge WCLK => (DOC : DIC)) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (posedge WCLK => (DOD : DID)) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
+        $setup(ADDRD[0], posedge WCLK, 362);
+        $setup(ADDRD[1], posedge WCLK, 245);
+        $setup(ADDRD[2], posedge WCLK, 208);
+        $setup(ADDRD[3], posedge WCLK, 147);
+        $setup(ADDRD[4], posedge WCLK, 68);
+        $setup(ADDRD[5], posedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA, posedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB, posedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC, posedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID, posedge WCLK, 310);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, posedge WCLK, 654);
+      endspecify
+    else
+      specify
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+        if (WE) (negedge WCLK => (DOA : DIA)) = 1153;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+        if (WE) (negedge WCLK => (DOB : DIB)) = 1161;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+        if (WE) (negedge WCLK => (DOC : DIC)) = 1158;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+        if (WE) (negedge WCLK => (DOD : DID)) = 1163;
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
+        $setup(ADDRD[0], negedge WCLK, 362);
+        $setup(ADDRD[1], negedge WCLK, 245);
+        $setup(ADDRD[2], negedge WCLK, 208);
+        $setup(ADDRD[3], negedge WCLK, 147);
+        $setup(ADDRD[4], negedge WCLK, 68);
+        $setup(ADDRD[5], negedge WCLK, 66);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+        $setup(DIA, negedge WCLK, 384);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+        $setup(DIB, negedge WCLK, 354);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+        $setup(DIC, negedge WCLK, 375);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+        $setup(DID, negedge WCLK, 310);
+        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+        $setup(WE, negedge WCLK, 654);
+      endspecify
+  endgenerate
 endmodule
 
 module RAM64M8 (

From 46a89d7264f597be9ad10390fa44c22e16538548 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Feb 2020 11:30:37 -0800
Subject: [PATCH 06/46] ecp5: deprecate abc9_{arrival,required} and *.{lut,box}

---
 techlibs/ecp5/Makefile.inc       |   3 -
 techlibs/ecp5/abc9_5g.box        |  36 ----------
 techlibs/ecp5/abc9_5g.lut        |  25 -------
 techlibs/ecp5/abc9_5g_nowide.lut |  12 ----
 techlibs/ecp5/abc9_model.v       |   9 ++-
 techlibs/ecp5/cells_sim.v        | 113 +++++++++++++++++++++++++++++--
 techlibs/ecp5/synth_ecp5.cc      |   8 +--
 7 files changed, 120 insertions(+), 86 deletions(-)
 delete mode 100644 techlibs/ecp5/abc9_5g.box
 delete mode 100644 techlibs/ecp5/abc9_5g.lut
 delete mode 100644 techlibs/ecp5/abc9_5g_nowide.lut

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 2c33f23b9..e4ee4991f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -18,9 +18,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/abc9_5g.box b/techlibs/ecp5/abc9_5g.box
deleted file mode 100644
index f153a665e..000000000
--- a/techlibs/ecp5/abc9_5g.box
+++ /dev/null
@@ -1,36 +0,0 @@
-# NB: Box inputs/outputs must each be in the same order
-#     as their corresponding module definition
-#     (with exceptions detailed below)
-
-# Box 1 : CCU2C (2xCARRY + 2xLUT4)
-#   (Exception: carry chain input/output must be the
-#        last input and output and the entire bus has been
-#        moved there overriding the otherwise
-#        alphabetical ordering)
-# name  ID   w/b   ins    outs
-CCU2C   1      1   9      3
-#A0  B0   C0    D0   A1   B1   C1   D1   CIN
-379  379  275   141  -    -    -    -    257 # S0
-630  630  526   392  379  379  275  141  273 # S1
-516  516  412   278  516  516  412  278   43 # COUT
-
-# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
-# name               ID  w/b   ins   outs
-$__ABC9_DPR16X4_COMB  2     0   8    4
-#$DO0 $DO1 $DO2 $DO3 RAD0   RAD1   RAD2   RAD3
-0     0    0    0    141    379    275    379 # DO0
-0     0    0    0    141    379    275    379 # DO1
-0     0    0    0    141    379    275    379 # DO2
-0     0    0    0    141    379    275    379 # DO3
-
-# Box 3 : PFUMX (MUX2)
-# name  ID   w/b   ins    outs
-PFUMX   3    1     3      1
-#ALUT  BLUT  C0
-98     98    151 # Z
-
-# Box 4 : L6MUX21 (MUX2)
-# name   ID   w/b   ins    outs
-L6MUX21  4    1     3      1
-#D0    D1    SD
-140    141   148 # Z
diff --git a/techlibs/ecp5/abc9_5g.lut b/techlibs/ecp5/abc9_5g.lut
deleted file mode 100644
index e8aa9b35d..000000000
--- a/techlibs/ecp5/abc9_5g.lut
+++ /dev/null
@@ -1,25 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-#  area  D    C    B    A
-1  1     141
-2  1     141  275
-3  1     141  275  379
-4  1     141  275  379  379
-
-# LUT5 = 2x LUT4 + PFUMX
-#  area  M0   D    C    B    A
-5  2     151  239  373  477  477
-
-# LUT6 = 2x LUT5 + MUX2
-#  area  M1   M0   D    C    B    A
-6  4     148  292  380  514  618  618
-
-# LUT7 = 2x LUT6 + MUX2
-#  area  M2   M1   M0   D    C    B    A
-7  8     148  289  433  521  655  759  759
-
diff --git a/techlibs/ecp5/abc9_5g_nowide.lut b/techlibs/ecp5/abc9_5g_nowide.lut
deleted file mode 100644
index 60352d892..000000000
--- a/techlibs/ecp5/abc9_5g_nowide.lut
+++ /dev/null
@@ -1,12 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-#  area  D    C    B    A
-1  1     141
-2  1     141  275
-3  1     141  275  379
-4  1     141  275  379  379
diff --git a/techlibs/ecp5/abc9_model.v b/techlibs/ecp5/abc9_model.v
index 81e5cd070..b7ecd7358 100644
--- a/techlibs/ecp5/abc9_model.v
+++ b/techlibs/ecp5/abc9_model.v
@@ -1,5 +1,12 @@
 // ---------------------------------------
 
-(* abc9_box_id=2 *)
+(* abc9_box *)
 module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
+  specify
+    ($DO => DO) = 0;
+    (RAD[0] *> DO) = 141;
+    (RAD[1] *> DO) = 379;
+    (RAD[2] *> DO) = 275;
+    (RAD[3] *> DO) = 379;
+  endspecify
 endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 0d3ec4e5b..ff6b8ccf9 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,22 +1,96 @@
 // ---------------------------------------
 
-(* lib_whitebox *)
+(* abc9_lut=1, lib_whitebox *)
 module LUT4(input A, B, C, D, output Z);
     parameter [15:0] INIT = 16'h0000;
     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
     wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
     wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
     assign Z =      A ?          s1[1] :         s1[0];
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+        (C => Z) = 379;
+        (D => Z) = 379;
+    endspecify
+endmodule
+
+(* abc9_lut=1 *)
+module \$__ABC9_LUT1 (input A, output Z);
+    specify
+        (A => Z) = 141;
+    endspecify
+endmodule
+
+(* abc9_lut=1 *)
+module \$__ABC9_LUT2 (input A, B, output Z);
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+    endspecify
+endmodule
+
+(* abc9_lut=1 *)
+module \$__ABC9_LUT3 (input A, B, C, output Z);
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+        (C => Z) = 379;
+    endspecify
+endmodule
+
+// LUT5 = 2x LUT4 + PFUMX
+(* abc9_lut=2 *)
+module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
+    specify
+        (M0 => Z) = 151;
+        (D => Z) = 239;
+        (C => Z) = 373;
+        (B => Z) = 477;
+        (A => Z) = 477;
+    endspecify
+endmodule
+
+// LUT6 = 2x LUT5 + MUX2
+(* abc9_lut=4 *)
+module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
+    specify
+        (M1 => Z) = 148;
+        (M0 => Z) = 292;
+        (D => Z) = 380;
+        (C => Z) = 514;
+        (B => Z) = 618;
+        (A => Z) = 618;
+    endspecify
+endmodule
+
+// LUT7 = 2x LUT6 + MUX2
+(* abc9_lut=8 *)
+module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
+    specify
+        (M2 => Z) = 148;
+        (M1 => Z) = 289;
+        (M0 => Z) = 433;
+        (D => Z) = 521;
+        (C => Z) = 655;
+        (B => Z) = 759;
+        (A => Z) = 759;
+    endspecify
 endmodule
 
 // ---------------------------------------
-(* abc9_box_id=4, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module L6MUX21 (input D0, D1, SD, output Z);
 	assign Z = SD ? D1 : D0;
+	specify
+		(D0 => Z) = 140;
+		(D1 => Z) = 141;
+		(SD => Z) = 148;
+	endspecify
 endmodule
 
 // ---------------------------------------
-(* abc9_box_id=1, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module CCU2C(
 	(* abc9_carry *)
 	input  CIN,
@@ -50,6 +124,31 @@ module CCU2C(
 	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
 	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
 
+	specify
+		(A0 => S0) = 379;
+		(B0 => S0) = 379;
+		(C0 => S0) = 275;
+		(D0 => S0) = 141;
+		(CIN => S0) = 257;
+		(A0 => S1) = 630;
+		(B0 => S1) = 630;
+		(C0 => S1) = 526;
+		(D0 => S1) = 392;
+		(A1 => S1) = 379;
+		(B1 => S1) = 379;
+		(C1 => S1) = 275;
+		(D1 => S1) = 141;
+		(CIN => S1) = 273;
+		(A0 => COUT) = 516;
+		(B0 => COUT) = 516;
+		(C0 => COUT) = 412;
+		(D0 => COUT) = 278;
+		(A1 => COUT) = 516;
+		(B1 => COUT) = 516;
+		(C1 => COUT) = 412;
+		(D1 => COUT) = 278;
+		(CIN => COUT) = 43;
+	endspecify
 endmodule
 
 // ---------------------------------------
@@ -94,9 +193,14 @@ module TRELLIS_RAM16X2 (
 endmodule
 
 // ---------------------------------------
-(* abc9_box_id=3, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module PFUMX (input ALUT, BLUT, C0, output Z);
 	assign Z = C0 ? ALUT : BLUT;
+	specify
+		(ALUT => Z) = 98;
+		(BLUT => Z) = 98;
+		(C0 => Z) = 151;
+	endspecify
 endmodule
 
 // ---------------------------------------
@@ -106,7 +210,6 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	/* (* abc9_arrival=<TODO> *) */
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index d47b2bed4..463ddb5ca 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+			run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
@@ -322,11 +322,11 @@ struct SynthEcp5Pass : public ScriptPass
 				run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
+				run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
+					run("abc9 -maxlut 4 -W 200");
 				else
-					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+					run("abc9 -W 200");
 				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)

From 12d70ca8fbad73f2615e711e786f8b90fa005bee Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Feb 2020 15:25:30 -0800
Subject: [PATCH 07/46] xilinx: improve specify functionality

---
 README.md                       |   7 +-
 backends/aiger/xaiger.cc        |   3 +
 passes/techmap/abc9_ops.cc      |  38 +-
 techlibs/xilinx/abc9_map.v      |  86 +++-
 techlibs/xilinx/abc9_model.v    |   6 +-
 techlibs/xilinx/abc9_unmap.v    |   4 +-
 techlibs/xilinx/cells_sim.v     | 865 ++++++++++++++++----------------
 techlibs/xilinx/synth_xilinx.cc |   4 +-
 8 files changed, 547 insertions(+), 466 deletions(-)

diff --git a/README.md b/README.md
index 8cd347497..08d4cb0d7 100644
--- a/README.md
+++ b/README.md
@@ -364,8 +364,13 @@ Verilog Attributes and non-standard features
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 
+- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9`
+  that this module describes a LUT with propagation delays described using
+  `specify` statements.
+
 - The module attribute ``abc9_box`` is a boolean specifying a blackbox or
-  whitebox definition for use by `abc9`.
+  whitebox definition, with propagation delays described using `specify`
+  statements, for use by `abc9`.
 
 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
   carry-out (if output port) ports of a box. This information is necessary for
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3cf36aca8..c996b0776 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -227,6 +227,9 @@ struct XAigerWriter
 					continue;
 				}
 
+				if (cell->type.in("$specify2", "$specify3", "$specrule"))
+					continue;
+
 				if (inst_module) {
 					bool abc9_flop = false;
 					auto it = cell->attributes.find("\\abc9_box_seq");
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9abe6af9f..c48cd5c86 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -380,8 +380,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design)
 {
-	// Derive and collect all blackbox modules, and collect all blackbox instantiations
-	pool<Module*> derived;
+	// Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
+	//   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
+	pool<Module*> blackboxes;
+	pool<Module*> flops;
 	std::vector<Cell*> cells;
 	for (auto module : design->selected_modules()) {
 		if (module->processes.size() > 0) {
@@ -400,42 +402,38 @@ void prep_delays(RTLIL::Design *design)
 				continue;
 			if (inst_module->attributes.count(ID(abc9_box)))
 				continue;
-			IdString derived_type = inst_module->derive(design, cell->parameters);
-			inst_module = design->module(derived_type);
+			IdString blackboxes_type = inst_module->derive(design, cell->parameters);
+			inst_module = design->module(blackboxes_type);
 			log_assert(inst_module);
-			derived.insert(inst_module);
+			blackboxes.insert(inst_module);
+
+			if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+				flops.insert(inst_module);
+				continue; // do not add $__ABC9_DELAY boxes to flops
+					  //   as delays will be captured in the flop box
+			}
 
 			cells.emplace_back(cell);
 		}
 	}
 
 	// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
-	std::vector<Module*> flops;
 	dict<SigBit, int> arrivals, requireds;
 	pool<Wire*> ports;
 	std::stringstream ss;
-	for (auto module : derived) {
-		if (module->get_bool_attribute(ID(abc9_flop)))
-			flops.push_back(module);
-
+	for (auto module : blackboxes) {
 		arrivals.clear();
 		requireds.clear();
 		for (auto cell : module->cells()) {
 			if (cell->type == ID($specify3)) {
 				auto src = cell->getPort(ID(SRC));
-				auto dat = cell->getPort(ID(DAT));
 				auto dst = cell->getPort(ID(DST));
 				for (const auto &c : src.chunks())
 					if (!c.wire->port_input)
 						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-				for (const auto &c : dat.chunks())
-					if (!c.wire->port_input)
-						log_error("Module '%s' contains specify cell '%s' where DAT '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dat));
 				for (const auto &c : dst.chunks())
 					if (!c.wire->port_output)
 						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-				if (!cell->getParam(ID(EDGE_EN)).as_bool())
-					continue;
 				int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
 				int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
 				int max = std::max(rise_max,fall_max);
@@ -443,7 +441,7 @@ void prep_delays(RTLIL::Design *design)
 					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
 					continue;
 				}
-				for (auto d : dst)
+				for (const auto &d : dst)
 					arrivals[d] = std::max(arrivals[d], max);
 			}
 			else if (cell->type == ID($specrule)) {
@@ -472,8 +470,10 @@ void prep_delays(RTLIL::Design *design)
 			continue;
 
 		ports.clear();
-		for (const auto &i : arrivals)
+		for (const auto &i : arrivals) {
+			log_dump(i.first, i.first.wire->name);
 			ports.insert(i.first.wire);
+		}
 		for (auto wire : ports) {
 			log_assert(wire->port_output);
 			ss.str("");
@@ -1239,7 +1239,7 @@ struct Abc9OpsPass : public Pass {
 		log("\n");
 		log("    -prep_box\n");
 		log("        pre-compute the box library by analysing all modules marked with\n");
-		log("        (* abc9_box *)\n");
+		log("        (* abc9_box *).\n");
 		log("\n");
 		log("    -write_box <dst>\n");
 		log("        write the pre-computed box library to <dst>.\n");
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index f2c401d66..53d9a3c9a 100644
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -398,8 +398,8 @@ module RAM32X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
   );
-  $__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
-  $__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
+  $__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
+  $__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM64X1D (
@@ -421,8 +421,8 @@ module RAM64X1D (
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
     .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
   );
-  $__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
-  $__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
+  $__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
+  $__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
 endmodule
 
 module RAM128X1D (
@@ -443,8 +443,8 @@ module RAM128X1D (
     .A(A),
     .DPRA(DPRA)
   );
-  $__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO));
-  $__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
+  $__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
+  $__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
 endmodule
 
 module RAM32M (
@@ -478,14 +478,14 @@ module RAM32M (
     .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
     .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
   );
-  $__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
-  $__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
-  $__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
-  $__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
-  $__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
-  $__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
-  $__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
-  $__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
+  $__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
+  $__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
+  $__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
+  $__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
+  $__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
+  $__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
+  $__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
+  $__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
 endmodule
 
 module RAM64M (
@@ -519,10 +519,25 @@ module RAM64M (
     .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
     .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
   );
-  $__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
-  $__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
-  $__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
-  $__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
+  $__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
+  $__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
+  $__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
+  $__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
+endmodule
+
+module SRL16 (
+  output Q,
+  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  wire $Q;
+  SRL16 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .Q($Q),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
+  );
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
 endmodule
 
 module SRL16E (
@@ -538,7 +553,38 @@ module SRL16E (
     .Q($Q),
     .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
   );
-  $__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+endmodule
+
+module SRLC16 (
+  output Q, Q15,
+  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  wire $Q;
+  SRLC16 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .Q($Q), .Q(Q15),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
+  );
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
+endmodule
+
+module SRLC16E (
+  output Q, Q15,
+  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
+);
+  parameter [15:0] INIT = 16'h0000;
+  parameter [0:0] IS_CLK_INVERTED = 1'b0;
+  wire $Q;
+  SRLC16E #(
+    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .Q($Q), .Q(Q15),
+    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+  );
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
 endmodule
 
 module SRLC32E (
@@ -556,7 +602,7 @@ module SRLC32E (
     .Q($Q), .Q31(Q31),
     .A(A), .CE(CE), .CLK(CLK), .D(D)
   );
-  $__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q));
+  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
 endmodule
 
 module DSP48E1 (
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 4373191ea..6beff30ba 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -55,6 +55,7 @@ module \$__ABC9_ASYNC0 (input A, S, output Y);
   assign Y = S ? 1'b0 : A;
   specify
     (A => Y) = 0;
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
     (S => Y) = 764;
   endspecify
 endmodule
@@ -65,6 +66,7 @@ module \$__ABC9_ASYNC1 (input A, S, output Y);
   assign Y = S ? 1'b1 : A;
   specify
     (A => Y) = 0;
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
     (S => Y) = 764;
   endspecify
 endmodule
@@ -76,7 +78,7 @@ endmodule
 //   To model the combinatorial path, such cells have to be split
 //   into comb and seq parts, with this box modelling only the former.
 (* abc9_box *)
-module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
+module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
   specify
     (S[0] => Y) = 642;
     (S[1] => Y) = 631;
@@ -88,7 +90,7 @@ module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
 endmodule
 // Box to emulate comb/seq behaviour of RAM128
 (* abc9_box *)
-module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
+module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
   specify
     (S[0] => Y) = 1028;
     (S[1] => Y) = 1017;
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v
index f2342ce62..c02cc196a 100644
--- a/techlibs/xilinx/abc9_unmap.v
+++ b/techlibs/xilinx/abc9_unmap.v
@@ -29,10 +29,10 @@ module $__ABC9_FF_(input D, output Q);
   assign Q = D;
 endmodule
 
-module $__ABC9_LUT6(input A, input [5:0] S, output Y);
+module $__ABC9_RAM6(input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
-module $__ABC9_LUT7(input A, input [6:0] S, output Y);
+module $__ABC9_RAM7(input A, input [6:0] S, output Y);
   assign Y = A;
 endmodule
 
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index f9d837e4c..08142b37f 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -263,46 +263,31 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
 endmodule
 
 (* abc9_lut=10 *)
-module $__ABC9_LUT7(output O, input I0, I1, I2, I3, I4, I5, I6);
-  parameter [127:0] INIT = 0;
-  wire [63: 0] s6 = I6 ? INIT[127:64] : INIT[63: 0];
-  wire [31: 0] s5 = I5 ?    s6[63:32] :   s6[31: 0];
-  wire [15: 0] s4 = I4 ?    s5[31:16] :   s5[15: 0];
-  wire [ 7: 0] s3 = I3 ?    s4[15: 8] :   s4[ 7: 0];
-  wire [ 3: 0] s2 = I2 ?    s3[ 7: 4] :   s3[ 3: 0];
-  wire [ 1: 0] s1 = I1 ?    s2[ 3: 2] :   s2[ 1: 0];
-  assign O = I0 ? s1[1] : s1[0];
+module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
   specify
-    (I0 => O) = 1028;
-    (I1 => O) = 1017;
-    (I2 => O) =  858;
-    (I3 => O) =  793;
-    (I4 => O) =  624;
-    (I5 => O) =  513;
-    (I6 => O) =  464;
+                                                 // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
+    (I0 => O) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I1 => O) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I2 => O) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I3 => O) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I4 => O) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I5 => O) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    (I6 => O) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
   endspecify
 endmodule
 
 (* abc9_lut=20 *)
-module $__ABC9_LUT8(output O, input I0, I1, I2, I3, I4, I5, I6, I7);
-  parameter [255:0] INIT = 0;
-  wire [127: 0] s7 = I7 ? INIT[255:128] : INIT[127: 0];
-  wire [ 63: 0] s6 = I6 ?   s7[127:63]  :   s7[ 64: 0];
-  wire [ 31: 0] s5 = I5 ?   s6[ 63:32]  :   s6[ 31: 0];
-  wire [ 15: 0] s4 = I4 ?   s5[ 31:16]  :   s5[ 15: 0];
-  wire [  7: 0] s3 = I3 ?   s4[ 15: 8]  :   s4[  7: 0];
-  wire [  3: 0] s2 = I2 ?   s3[  7: 4]  :   s3[  3: 0];
-  wire [  1: 0] s1 = I1 ?   s2[  3: 2]  :   s2[  1: 0];
-  assign O = I0 ? s1[1] : s1[0];
+module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
   specify
-    (I0 => O) = 1149;
-    (I1 => O) = 1138;
-    (I2 => O) =  979;
-    (I3 => O) =  914;
-    (I4 => O) =  745;
-    (I5 => O) =  634;
-    (I6 => O) =  585;
-    (I7 => O) =  468;
+                                                                             // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716
+    (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I6 => O) = 0 + 296 /* to select F7BMUX */  + 104 /* to cross F8MUX */ + 192 /* BMUX */;
+    (I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */;
   endspecify
 endmodule
 
@@ -323,9 +308,9 @@ module MUXF7(output O, input I0, I1, S);
   assign O = S ? I1 : I0;
   specify
     // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L451-L453
-    (I0 => O) = 204;
-    (I1 => O) = 208;
-    (S => O) = 286;
+    (I0 => O) = 217;
+    (I1 => O) = 223;
+    (S => O) = 296;
   endspecify
 endmodule
 
@@ -497,21 +482,23 @@ module FDRE (
     1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //$setup(D , posedge C, -46); // Negative times not currently supported
-      $setup(CE, posedge C, 109);
-      $setup(R , posedge C, 404);
-    endspecify
-  else
-    specify
-      if (CE) (negedge C => (Q : D)) = 303;
-      //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
-      $setup(CE, negedge C, 109);
-      $setup(R , negedge C, 404);
-    endspecify
   endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& CE &&& !IS_C_INVERTED , -46); // Negative times not currently supported
+    //$setup(D , negedge C &&& CE &&&  IS_C_INVERTED , -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE, negedge C &&&  IS_C_INVERTED , 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
+    $setup(R , posedge C &&& !IS_C_INVERTED, 404);
+    $setup(R , negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (!IS_C_INVERTED && R ^ IS_R_INVERTED)        (posedge C => (Q : 1'b0)) = 303;
+    if ( IS_C_INVERTED && R ^ IS_R_INVERTED)        (negedge C => (Q : 1'b0)) = 303;
+    if (!IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && R ~^ IS_R_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -527,10 +514,14 @@ module FDRE_1 (
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, negedge C, 109);
-    $setup(R , negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
+    $setup(R , negedge C, 404);    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (R)        (negedge C => (Q : 1'b0)) = 303;
+    if (!R && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -556,21 +547,23 @@ module FDSE (
     1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //if (CE) $setup(D , posedge C, -46); // Negative times not currently supported
-      $setup(CE, posedge C, 109);
-      $setup(S , posedge C, 404);
-    endspecify
-  else
-    specify
-        if (CE) (negedge C => (Q : D)) = 303;
-        //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
-        $setup(CE, negedge C, 109);
-        $setup(S , negedge C, 404);
-    endspecify
   endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE, negedge C &&&  IS_C_INVERTED, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
+    $setup(S , posedge C &&& !IS_C_INVERTED, 404);
+    $setup(S , negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (!IS_C_INVERTED && S ^ IS_S_INVERTED)        (posedge C => (Q : 1'b1)) = 303;
+    if ( IS_C_INVERTED && S ^ IS_S_INVERTED)        (negedge C => (Q : 1'b1)) = 303;
+    if (!IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && S ~^ IS_S_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -586,10 +579,15 @@ module FDSE_1 (
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, negedge C, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(S , negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf#L243
+    if (S)        (negedge C => (Q : 1'b1)) = 303;
+    if (!S && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -652,21 +650,22 @@ module FDCE (
     2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
-      $setup(CE , posedge C, 109);
-      $setup(CLR, posedge C, 764);
-    endspecify
-  else
-    specify
-        if (CE) (negedge C => (Q : D)) = 303;
-        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
-        $setup(CE , negedge C, 109);
-        $setup(CLR, negedge C, 764);
-    endspecify
- endgenerate
+  endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
+    $setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
+    $setup(CLR, negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //if (!IS_CLR_INVERTED) (posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    //if ( IS_CLR_INVERTED) (negedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    if (!IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && CLR ~^ IS_CLR_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -682,10 +681,14 @@ module FDCE_1 (
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , negedge C, 109);
-    $setup(CLR, negedge C, 764);
+    $setup(CLR, negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
+    if (!CLR && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -712,21 +715,22 @@ module FDPE (
     2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
     2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
   endcase
-  if (!IS_C_INVERTED)
-    specify
-      if (CE) (posedge C => (Q : D)) = 303;
-      //if (CE) $setup(D  , posedge C, -46); // Negative times not currently supported
-      $setup(CE , posedge C, 109);
-      $setup(PRE, posedge C, 764);
-    endspecify
-  else
-    specify
-        if (CE) (negedge C => (Q : D)) = 303;
-        //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
-        $setup(CE , negedge C, 109);
-        $setup(PRE, negedge C, 764);
-    endspecify
   endgenerate
+  specify
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
+    $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
+    $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
+    $setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
+    $setup(PRE, negedge C &&&  IS_C_INVERTED, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    //if ( IS_PRE_INVERTED) (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    if (!IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (posedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+    if ( IS_C_INVERTED && PRE ~^ IS_PRE_INVERTED && CE) (negedge C => (Q : D ^ IS_D_INVERTED)) = 303;
+  endspecify
 endmodule
 
 (* abc9_flop, lib_whitebox *)
@@ -742,10 +746,15 @@ module FDPE_1 (
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
   specify
-    if (CE) (negedge C => (Q : D)) = 303;
-    //if (CE) $setup(D  , negedge C, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
+    //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , negedge C, 109);
-    $setup(PRE, negedge C, 764);
+    $setup(PRE, negedge C, 404);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
+    //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    //if (IS_PRE_INVERTED)  (negedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1
+    if (!PRE && CE) (negedge C => (Q : D)) = 303;
   endspecify
 endmodule
 
@@ -1375,48 +1384,38 @@ module RAM32X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (posedge WCLK => (SPO : D)) = 1153;
-        if (WE) (posedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , posedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-        $setup(A0, posedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-        $setup(A1, posedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-        $setup(A2, posedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-        $setup(A3, posedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-        $setup(A4, posedge WCLK, 66);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (negedge WCLK => (SPO : D)) = 1153;
-        if (WE) (negedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , negedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-        $setup(A0, negedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-        $setup(A1, negedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-        $setup(A2, negedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-        $setup(A3, negedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-        $setup(A4, negedge WCLK, 66);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
+    $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(A0, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
+    $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(A1, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
+    $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(A2, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
+    $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(A3, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
+    $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(A4, posedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    // Captured by $__ABC9_RAM6
+    //({A0,DPRA0} => {SPO,DPO}) = 642;
+    //({A1,DPRA1} => {SPO,DPO}) = 631;
+    //({A2,DPRA2} => {SPO,DPO}) = 472;
+    //({A3,DPRA3} => {SPO,DPO}) = 407;
+    //({A4,DPRA4} => {SPO,DPO}) = 238;
+  endspecify
 endmodule
 
 module RAM32X1D_1 (
@@ -1443,23 +1442,28 @@ module RAM32X1D_1 (
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
   specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => (SPO : D)) = 1153;
-    if (WE) (negedge WCLK => (DPO : D)) = 1153;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , negedge WCLK, 453);
+    $setup(D , negedge WCLK &&& WE, 453);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
     $setup(WE, negedge WCLK, 654);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L800
-    $setup(A0, negedge WCLK, 245);
+    $setup(A0, negedge WCLK &&& WE, 245);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L798
-    $setup(A1, negedge WCLK, 208);
+    $setup(A1, negedge WCLK &&& WE, 208);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L796
-    $setup(A2, negedge WCLK, 147);
+    $setup(A2, negedge WCLK &&& WE, 147);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L794
-    $setup(A3, negedge WCLK, 68);
+    $setup(A3, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
-    $setup(A4, negedge WCLK, 66);
+    $setup(A4, negedge WCLK &&& WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    // Captured by $__ABC9_RAM6
+    //({A0,DPRA0} => {SPO,DPO}) = 642;
+    //({A1,DPRA1} => {SPO,DPO}) = 631;
+    //({A2,DPRA2} => {SPO,DPO}) = 472;
+    //({A3,DPRA3} => {SPO,DPO}) = 407;
+    //({A4,DPRA4} => {SPO,DPO}) = 238;
   endspecify
 endmodule
 
@@ -1482,52 +1486,42 @@ module RAM64X1D (
   assign DPO = mem[dpra];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (posedge WCLK => (SPO : D)) = 1153;
-        if (WE) (posedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , posedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-        $setup(A0, posedge WCLK, 362);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-        $setup(A1, posedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-        $setup(A2, posedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-        $setup(A3, posedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-        $setup(A4, posedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-        $setup(A5, posedge WCLK, 66);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        if (WE) (negedge WCLK => (SPO : D)) = 1153;
-        if (WE) (negedge WCLK => (DPO : D)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , negedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-        $setup(A0, negedge WCLK, 362);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-        $setup(A1, negedge WCLK, 245);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-        $setup(A2, negedge WCLK, 208);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-        $setup(A3, negedge WCLK, 147);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-        $setup(A4, negedge WCLK, 68);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-        $setup(A5, negedge WCLK, 66);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
+    $setup(A0, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
+    $setup(A0, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
+    $setup(A1, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(A1, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
+    $setup(A2, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(A2, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
+    $setup(A3, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(A3, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
+    $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(A4, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
+    $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(A5, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+    // Captured by $__ABC9_RAM6
+    //({A0,DPRA0} => {SPO,DPO}) = 642;
+    //({A1,DPRA1} => {SPO,DPO}) = 631;
+    //({A2,DPRA2} => {SPO,DPO}) = 472;
+    //({A3,DPRA3} => {SPO,DPO}) = 407;
+    //({A4,DPRA4} => {SPO,DPO}) = 238;
+    //({A5,DPRA5} => {SPO,DPO}) = 127;
+  endspecify
 endmodule
 
 module RAM64X1D_1 (
@@ -1550,25 +1544,24 @@ module RAM64X1D_1 (
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(negedge clk) if (WE) mem[a] <= D;
   specify
-    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => (SPO : D)) = 1153;
-    if (WE) (negedge WCLK => (DPO : D)) = 1153;
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-    $setup(D , negedge WCLK, 453);
+    $setup(D , negedge WCLK &&& WE, 453);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
     $setup(WE, negedge WCLK, 654);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L828
-    $setup(A0, negedge WCLK, 362);
+    $setup(A0, negedge WCLK &&& WE, 362);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L826
-    $setup(A1, negedge WCLK, 245);
+    $setup(A1, negedge WCLK &&& WE, 245);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L824
-    $setup(A2, negedge WCLK, 208);
+    $setup(A2, negedge WCLK &&& WE, 208);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L822
-    $setup(A3, negedge WCLK, 147);
+    $setup(A3, negedge WCLK &&& WE, 147);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L820
-    $setup(A4, negedge WCLK, 68);
+    $setup(A4, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
-    $setup(A5, negedge WCLK, 66);
+    $setup(A5, negedge WCLK &&& WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
   endspecify
 endmodule
 
@@ -1579,8 +1572,6 @@ module RAM128X1D (
   (* invertible_pin = "IS_WCLK_INVERTED" *)
   input        WCLK,
   input        WE,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-  (* abc9_required="616 362 245 208 147 68 66" *)
   input  [6:0] A,
   input  [6:0] DPRA
 );
@@ -1591,46 +1582,47 @@ module RAM128X1D (
   assign DPO = mem[DPRA];
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        //   plus 208ps to cross MUXF7
-        if (WE) (posedge WCLK => (SPO : D)) = 1359;
-        if (WE) (posedge WCLK => (DPO : D)) = 1359;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , posedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-        $setup(A[0], posedge WCLK, 616);
-        $setup(A[1], posedge WCLK, 362);
-        $setup(A[2], posedge WCLK, 245);
-        $setup(A[3], posedge WCLK, 208);
-        $setup(A[4], posedge WCLK, 147);
-        $setup(A[5], posedge WCLK, 68);
-        $setup(A[6], posedge WCLK, 66);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-        //   plus 208ps to cross MUXF7
-        if (WE) (negedge WCLK => (SPO : D)) = 1359;
-        if (WE) (negedge WCLK => (DPO : D)) = 1359;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(D , negedge WCLK, 453);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
-        $setup(A[0], negedge WCLK, 616);
-        $setup(A[1], negedge WCLK, 362);
-        $setup(A[2], negedge WCLK, 245);
-        $setup(A[3], negedge WCLK, 208);
-        $setup(A[4], negedge WCLK, 147);
-        $setup(A[5], negedge WCLK, 68);
-        $setup(A[6], negedge WCLK, 66);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(D , posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(D , negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-830
+    $setup(A[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 616);
+    $setup(A[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 616);
+    $setup(A[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
+    $setup(A[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
+    $setup(A[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(A[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    $setup(A[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(A[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    $setup(A[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(A[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    $setup(A[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(A[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    $setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(A[6], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    // Captured by $__ABC9_RAM7
+    //(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[2] => SPO) = 472 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[3] => SPO) = 407 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[4] => SPO) = 238 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[5] => SPO) = 127 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
+    //(A[6] => SPO) = 0 + 276 /* to select F7AMUX */ + 175 /* AMUX */;
+    //(DPRA[0] => DPO) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[1] => DPO) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[2] => DPO) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[3] => DPO) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[4] => DPO) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[5] => DPO) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
+    //(DPRA[6] => DPO) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
+  endspecify
 endmodule
 
 module RAM256X1D (
@@ -1690,87 +1682,72 @@ module RAM32M (
       mem_c[2*ADDRD+:2] <= DIC;
       mem_d[2*ADDRD+:2] <= DID;
     end
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-        if (WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-        if (WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-        if (WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-        if (WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(ADDRD[0], posedge WCLK, 245);
-        $setup(ADDRD[1], posedge WCLK, 208);
-        $setup(ADDRD[2], posedge WCLK, 147);
-        $setup(ADDRD[3], posedge WCLK, 68);
-        $setup(ADDRD[4], posedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA[0], posedge WCLK, 453);
-        $setup(DIA[1], posedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB[0], posedge WCLK, 461);
-        $setup(DIB[1], posedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC[0], posedge WCLK, 457);
-        $setup(DIC[1], posedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID[0], posedge WCLK, 310);
-        $setup(DID[1], posedge WCLK, 334);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
-        if (WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
-        if (WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
-        if (WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
-        if (WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
-        $setup(ADDRD[0], negedge WCLK, 245);
-        $setup(ADDRD[1], negedge WCLK, 208);
-        $setup(ADDRD[2], negedge WCLK, 147);
-        $setup(ADDRD[3], negedge WCLK, 68);
-        $setup(ADDRD[4], negedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA[0], negedge WCLK, 453);
-        $setup(DIA[1], negedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB[0], negedge WCLK, 461);
-        $setup(DIB[1], negedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC[0], negedge WCLK, 457);
-        $setup(DIC[1], negedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID[0], negedge WCLK, 310);
-        $setup(DID[1], negedge WCLK, 334);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-      endspecify
-  endgenerate
-
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986
+    $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(ADDRD[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+    $setup(DIA[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 453);
+    $setup(DIA[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 453);
+    $setup(DIA[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
+    $setup(DIA[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 384);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+    $setup(DIB[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 461);
+    $setup(DIB[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 461);
+    $setup(DIB[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
+    $setup(DIB[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 354);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+    $setup(DIC[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 457);
+    $setup(DIC[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 457);
+    $setup(DIC[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
+    $setup(DIC[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 375);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+    $setup(DID[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
+    $setup(DID[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 310);
+    $setup(DID[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 334);
+    $setup(DID[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 334);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[0] : DIA[0])) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[0] : DIA[0])) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L857
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA[1] : DIA[1])) = 1188;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA[1] : DIA[1])) = 1188;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[0] : DIB[0])) = 1161;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[0] : DIB[0])) = 1161;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L925
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB[1] : DIB[1])) = 1187;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB[1] : DIB[1])) = 1187;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L993
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[0] : DIC[0])) = 1158;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[0] : DIC[0])) = 1158;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC[1] : DIC[1])) = 1180;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC[1] : DIC[1])) = 1180;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[0] : DID[0])) = 1163;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[0] : DID[0])) = 1163;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1061
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD[1] : DID[1])) = 1190;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD[1] : DID[1])) = 1190;
+    // Captured by $__ABC9_RAM6
+    //({{2{ADDRA[0]}},{2{ADDRB[0]}},{2{ADDRC[0]}},{2{ADDRD[0]}}} => {DOA,DOB,DOC,DOD}) = 642;
+    //({{2{ADDRA[1]}},{2{ADDRB[1]}},{2{ADDRC[1]}},{2{ADDRD[1]}}} => {DOA,DOB,DOC,DOD}) = 631;
+    //({{2{ADDRA[2]}},{2{ADDRB[2]}},{2{ADDRC[2]}},{2{ADDRD[2]}}} => {DOA,DOB,DOC,DOD}) = 472;
+    //({{2{ADDRA[3]}},{2{ADDRB[3]}},{2{ADDRC[3]}},{2{ADDRD[3]}}} => {DOA,DOB,DOC,DOD}) = 407;
+    //({{2{ADDRA[4]}},{2{ADDRB[4]}},{2{ADDRC[4]}},{2{ADDRD[4]}}} => {DOA,DOB,DOC,DOD}) = 238;
+  endspecify
 endmodule
 
 module RAM32M16 (
@@ -1879,64 +1856,54 @@ module RAM64M (
       mem_c[ADDRD] <= DIC;
       mem_d[ADDRD] <= DID;
     end
-  generate
-    if (!IS_WCLK_INVERTED)
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (posedge WCLK => (DOA : DIA)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (posedge WCLK => (DOB : DIB)) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (posedge WCLK => (DOC : DIC)) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (posedge WCLK => (DOD : DID)) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-        $setup(ADDRD[0], posedge WCLK, 362);
-        $setup(ADDRD[1], posedge WCLK, 245);
-        $setup(ADDRD[2], posedge WCLK, 208);
-        $setup(ADDRD[3], posedge WCLK, 147);
-        $setup(ADDRD[4], posedge WCLK, 68);
-        $setup(ADDRD[5], posedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA, posedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB, posedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC, posedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID, posedge WCLK, 310);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, posedge WCLK, 654);
-      endspecify
-    else
-      specify
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
-        if (WE) (negedge WCLK => (DOA : DIA)) = 1153;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-        if (WE) (negedge WCLK => (DOB : DIB)) = 1161;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
-        if (WE) (negedge WCLK => (DOC : DIC)) = 1158;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
-        if (WE) (negedge WCLK => (DOD : DID)) = 1163;
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
-        $setup(ADDRD[0], negedge WCLK, 362);
-        $setup(ADDRD[1], negedge WCLK, 245);
-        $setup(ADDRD[2], negedge WCLK, 208);
-        $setup(ADDRD[3], negedge WCLK, 147);
-        $setup(ADDRD[4], negedge WCLK, 68);
-        $setup(ADDRD[5], negedge WCLK, 66);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
-        $setup(DIA, negedge WCLK, 384);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
-        $setup(DIB, negedge WCLK, 354);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
-        $setup(DIC, negedge WCLK, 375);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
-        $setup(DID, negedge WCLK, 310);
-        // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
-        $setup(WE, negedge WCLK, 654);
-      endspecify
-  endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818-L830
+    $setup(ADDRD[0], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 362);
+    $setup(ADDRD[0], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 362);
+    $setup(ADDRD[1], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[1], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 245);
+    $setup(ADDRD[2], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[2], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 208);
+    $setup(ADDRD[3], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[3], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 147);
+    $setup(ADDRD[4], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[4], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
+    $setup(ADDRD[5], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
+    $setup(ADDRD[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L986-L988
+    $setup(DIA, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 384);
+    $setup(DIA, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 384);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1054-L1056
+    $setup(DIB, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 354);
+    $setup(DIB, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 354);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1122-L1124
+    $setup(DIC, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 375);
+    $setup(DIC, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 375);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L1190-L1192
+    $setup(DID, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 310);
+    $setup(DID, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 310);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L834
+    $setup(WE, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 654);
+    $setup(WE, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 654);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L889
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOA : DIA)) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOA : DIA)) = 1153;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOB : DIB)) = 1161;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOB : DIB)) = 1161;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1025
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOC : DIC)) = 1158;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOC : DIC)) = 1158;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L1093
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DOD : DID)) = 1163;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DOD : DID)) = 1163;
+    // Captured by $__ABC9_RAM6
+    //({ADDRA[0],ADDRB[0],ADDRC[0],ADDRD[0]} => {DOA,DOB,DOC,DOD}) = 642;
+    //({ADDRA[1],ADDRB[1],ADDRC[1],ADDRD[1]} => {DOA,DOB,DOC,DOD}) = 631;
+    //({ADDRA[2],ADDRB[2],ADDRC[2],ADDRD[2]} => {DOA,DOB,DOC,DOD}) = 472;
+    //({ADDRA[3],ADDRB[3],ADDRC[3],ADDRD[3]} => {DOA,DOB,DOC,DOD}) = 407;
+    //({ADDRA[4],ADDRB[4],ADDRC[4],ADDRD[4]} => {DOA,DOB,DOC,DOD}) = 238;
+  endspecify
 endmodule
 
 module RAM64M8 (
@@ -2064,11 +2031,21 @@ module SRL16 (
   reg [15:0] r = INIT;
   assign Q = r[{A3,A2,A1,A0}];
   always @(posedge CLK) r <= { r[14:0], D };
+
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    (posedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK, 173);
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 631;
+    //(A1 => Q) = 472;
+    //(A2 => Q) = 407;
+    //(A3 => Q) = 238;
+  endspecify
 endmodule
 
 module SRL16E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
-  (* abc9_arrival=1472 *)
   output Q,
   input A0, A1, A2, A3, CE,
   (* clkbuf_sink *)
@@ -2088,6 +2065,19 @@ module SRL16E (
     else
       always @(posedge CLK) if (CE) r <= { r[14:0], D };
   endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
+    $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 631;
+    //(A1 => Q) = 472;
+    //(A2 => Q) = 407;
+    //(A3 => Q) = 238;
+  endspecify
 endmodule
 
 module SRLC16 (
@@ -2104,6 +2094,18 @@ module SRLC16 (
   assign Q15 = r[15];
   assign Q = r[{A3,A2,A1,A0}];
   always @(posedge CLK) r <= { r[14:0], D };
+
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    (posedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK, 173);
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 631;
+    //(A1 => Q) = 472;
+    //(A2 => Q) = 407;
+    //(A3 => Q) = 238;
+  endspecify
 endmodule
 
 module SRLC16E (
@@ -2128,14 +2130,24 @@ module SRLC16E (
     else
       always @(posedge CLK) if (CE) r <= { r[14:0], D };
   endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
+    $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : D)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : D)) = 1472;
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 642;
+    //(A1 => Q) = 631;
+    //(A2 => Q) = 472;
+    //(A3 => Q) = 407;
+    //(A4 => Q) = 238;
+  endspecify
 endmodule
 
 module SRLC32E (
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
-  (* abc9_arrival=1472 *)
   output Q,
-  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
-  (* abc9_arrival=1114 *)
   output Q31,
   input [4:0] A,
   input CE,
@@ -2157,6 +2169,23 @@ module SRLC32E (
     else
       always @(posedge CLK) if (CE) r <= { r[30:0], D };
   endgenerate
+  specify
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L912
+    $setup(D , posedge CLK &&& !IS_CLK_INVERTED, 173);
+    $setup(D , negedge CLK &&&  IS_CLK_INVERTED, 173);
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L905
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1472;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1472;
+    // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904
+    if (!IS_CLK_INVERTED && CE) (posedge CLK => (Q : 1'bx)) = 1114;
+    if ( IS_CLK_INVERTED && CE) (negedge CLK => (Q : 1'bx)) = 1114;
+    // Captured by $__ABC9_RAM6
+    //(A0 => Q) = 642;
+    //(A1 => Q) = 631;
+    //(A2 => Q) = 472;
+    //(A3 => Q) = 407;
+    //(A4 => Q) = 238;
+  endspecify
 endmodule
 
 module CFGLUT5 (
@@ -2928,31 +2957,16 @@ module DSP48E1 (
     output reg [3:0] CARRYOUT,
     output reg MULTSIGNOUT,
     output OVERFLOW,
-`ifdef YOSYS
-    (* abc9_arrival = \P.abc9_arrival () *)
-`endif
     output reg signed [47:0] P,
     output reg PATTERNBDETECT,
     output reg PATTERNDETECT,
-`ifdef YOSYS
-    (* abc9_arrival = \PCOUT.abc9_arrival () *)
-`endif
     output [47:0] PCOUT,
     output UNDERFLOW,
-`ifdef YOSYS
-    (* abc9_required = \A.abc9_required () *)
-`endif
     input signed [29:0] A,
     input [29:0] ACIN,
     input [3:0] ALUMODE,
-`ifdef YOSYS
-    (* abc9_required = \B.abc9_required () *)
-`endif
     input signed [17:0] B,
     input [17:0] BCIN,
-`ifdef YOSYS
-    (* abc9_required = \C.abc9_required () *)
-`endif
     input [47:0] C,
     input CARRYCASCIN,
     input CARRYIN,
@@ -2971,16 +2985,10 @@ module DSP48E1 (
     input CEM,
     input CEP,
     (* clkbuf_sink *) input CLK,
-`ifdef YOSYS
-    (* abc9_required = \D.abc9_required () *)
-`endif
     input [24:0] D,
     input [4:0] INMODE,
     input MULTSIGNIN,
     input [6:0] OPMODE,
-`ifdef YOSYS
-    (* abc9_required = \PCIN.abc9_required () *)
-`endif
     input [47:0] PCIN,
     input RSTA,
     input RSTALLCARRYIN,
@@ -3157,6 +3165,23 @@ module DSP48E1 (
         //    $error("Invalid DSP48E1 configuration");
     end
     endfunction
+
+    specify
+        $setup(A   , posedge CLK &&& !IS_CLK_INVERTED, \A.abc9_required () );
+        $setup(A   , negedge CLK &&&  IS_CLK_INVERTED, \A.abc9_required () );
+        $setup(B   , posedge CLK &&& !IS_CLK_INVERTED, \B.abc9_required () );
+        $setup(B   , negedge CLK &&&  IS_CLK_INVERTED, \B.abc9_required () );
+        $setup(C   , posedge CLK &&& !IS_CLK_INVERTED, \C.abc9_required () );
+        $setup(C   , negedge CLK &&&  IS_CLK_INVERTED, \C.abc9_required () );
+        $setup(D   , posedge CLK &&& !IS_CLK_INVERTED, \D.abc9_required () );
+        $setup(D   , negedge CLK &&&  IS_CLK_INVERTED, \D.abc9_required () );
+        $setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, \PCIN.abc9_required () );
+        $setup(PCIN, negedge CLK &&&  IS_CLK_INVERTED, \PCIN.abc9_required () );
+        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.abc9_arrival () ;
+        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.abc9_arrival () ;
+        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.abc9_arrival () ;
+        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.abc9_arrival () ;
+    endspecify
 `endif
 
     initial begin
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4011e09b0..bb3ced8da 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,8 +619,8 @@ struct SynthXilinxPass : public ScriptPass
 				if (dff_mode)
 					techmap_args += " -D DFF_MODE";
 				run("techmap " + techmap_args);
-				run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v");
-				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
+				run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
+				std::string abc9_opts;
 				auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
 				if (active_design->scratchpad.count(k))
 					abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());

From ccc84f89235c867544ce5d93802f435ec35ec076 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Feb 2020 16:06:24 -0800
Subject: [PATCH 08/46] Fix commented out specify statement

---
 techlibs/xilinx/cells_sim.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 08142b37f..1851f1ddc 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -550,8 +550,8 @@ module FDSE (
   endgenerate
   specify
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
-    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
-    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED && CE, -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
     $setup(CE, negedge C &&&  IS_C_INVERTED, 109);
@@ -653,8 +653,8 @@ module FDCE (
   endgenerate
   specify
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
-    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
-    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED && CE, -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
     $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
@@ -718,8 +718,8 @@ module FDPE (
   endgenerate
   specify
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
-    //$setup(D , posedge C &&& !IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
-    //$setup(D , negedge C &&&  IS_C_INVERTED &&& CE, -46); // Negative times not currently supported
+    //$setup(D , posedge C &&& !IS_C_INVERTED && CE, -46); // Negative times not currently supported
+    //$setup(D , negedge C &&&  IS_C_INVERTED && CE, -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
     $setup(CE , negedge C &&&  IS_C_INVERTED, 109);

From 0ed550d83c6d4b4ff4301ee5316d5840fd36b72e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:48:48 -0800
Subject: [PATCH 09/46] abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and
 auto-gen small LUTs

---
 passes/techmap/abc9_ops.cc | 51 ++++++++++++++++++++++++--------------
 1 file changed, 33 insertions(+), 18 deletions(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index c48cd5c86..c202d3d66 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -437,8 +437,10 @@ void prep_delays(RTLIL::Design *design)
 				int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
 				int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
 				int max = std::max(rise_max,fall_max);
-				if (max < 0) {
+				if (max < 0)
 					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+				if (max <= 0) {
+					log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
 					continue;
 				}
 				for (const auto &d : dst)
@@ -456,9 +458,11 @@ void prep_delays(RTLIL::Design *design)
 				for (const auto &c : dst.chunks())
 					if (!c.wire->port_input)
 						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
-				int setup = cell->getParam(ID(T_LIMIT)).as_int();
-				if (setup < 0) {
-					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+				int setup = cell->getParam(ID(T_LIMIT_MAX)).as_int();
+				if (setup < 0)
+					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+				if (setup <= 0) {
+					log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
 					continue;
 				}
 				for (const auto &s : src)
@@ -582,8 +586,7 @@ void prep_delays(RTLIL::Design *design)
 
 void prep_lut(RTLIL::Design *design, int maxlut)
 {
-	std::stringstream ss;
-	std::vector<std::pair<int, std::string>> table;
+	std::vector<std::tuple<int, IdString, std::vector<int>>> table;
 	for (auto module : design->modules()) {
 		auto it = module->attributes.find(ID(abc9_lut));
 		if (it == module->attributes.end())
@@ -603,6 +606,8 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 				o = d;
 			else
 				log_assert(o == d);
+			// TODO: Don't assume that each specify entry with the destination 'o'
+			//       describes a unique LUT input
 			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
 			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
 			int max = std::max(rise_max,fall_max);
@@ -612,20 +617,30 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		}
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
-		std::sort(specify.begin(), specify.end());
-		ss.str("");
-		ss << "# " << module->name.str() << std::endl;
-		ss << GetSize(specify) << " " << it->second.as_int();
-		for (auto i : specify)
-			ss << " " << i;
-		ss << std::endl;
-		table.emplace_back(GetSize(specify), ss.str());
+		// ABC requires ascending LUT input delays
+		table.emplace_back(GetSize(specify), module->name, std::move(specify));
 	}
-	// ABC expects ascending size
+	// ABC requires ascending size
 	std::sort(table.begin(), table.end());
-	ss.str("");
-	for (auto &i : table)
-		ss << i.second;
+
+	std::stringstream ss;
+	const auto &first = table.front();
+	// If the first entry does not start from a 1-input LUT,
+	//   (as ABC requires) crop the first entry to do so
+	for (int i = 1; i < std::get<0>(first); i++) {
+		ss << "# $__ABC9_LUT" << i << std::endl;
+		ss << i;
+		for (int j = 0; j < i; j++)
+			ss << " " << std::get<2>(first)[j];
+		ss << std::endl;
+	}
+	for (const auto &i : table) {
+		ss << "# " << log_id(std::get<1>(i)) << std::endl;
+		ss << GetSize(std::get<2>(i));
+		for (const auto &j : std::get<2>(i))
+			ss << " " << j;
+		ss << std::endl;
+	}
 	design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
 }
 

From d2284715fa3399b9afe8609a1035e563393a21b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:50:17 -0800
Subject: [PATCH 10/46] ecp5: remove small LUT entries

---
 techlibs/ecp5/cells_sim.v | 30 ++++++------------------------
 1 file changed, 6 insertions(+), 24 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ff6b8ccf9..12b33e925 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -15,30 +15,8 @@ module LUT4(input A, B, C, D, output Z);
     endspecify
 endmodule
 
-(* abc9_lut=1 *)
-module \$__ABC9_LUT1 (input A, output Z);
-    specify
-        (A => Z) = 141;
-    endspecify
-endmodule
-
-(* abc9_lut=1 *)
-module \$__ABC9_LUT2 (input A, B, output Z);
-    specify
-        (A => Z) = 141;
-        (B => Z) = 275;
-    endspecify
-endmodule
-
-(* abc9_lut=1 *)
-module \$__ABC9_LUT3 (input A, B, C, output Z);
-    specify
-        (A => Z) = 141;
-        (B => Z) = 275;
-        (C => Z) = 379;
-    endspecify
-endmodule
-
+// This is a placeholder for ABC9 to extract the area/delay
+//   cost of 5-input LUTs and is not intended to be instantiated
 // LUT5 = 2x LUT4 + PFUMX
 (* abc9_lut=2 *)
 module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
@@ -51,6 +29,8 @@ module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
     endspecify
 endmodule
 
+// This is a placeholder for ABC9 to extract the area/delay
+//   of 6-input LUTs and is not intended to be instantiated
 // LUT6 = 2x LUT5 + MUX2
 (* abc9_lut=4 *)
 module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
@@ -64,6 +44,8 @@ module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
     endspecify
 endmodule
 
+// This is a placeholder for ABC9 to extract the area/delay
+//   of 7-input LUTs and is not intended to be instantiated
 // LUT7 = 2x LUT6 + MUX2
 (* abc9_lut=8 *)
 module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);

From 7317521c6fa897c90328ac127cb0cf98de0bb7dd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:54:40 -0800
Subject: [PATCH 11/46] abc9_ops: output LUT area

---
 passes/techmap/abc9_ops.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index c202d3d66..61a3880b7 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -586,7 +586,7 @@ void prep_delays(RTLIL::Design *design)
 
 void prep_lut(RTLIL::Design *design, int maxlut)
 {
-	std::vector<std::tuple<int, IdString, std::vector<int>>> table;
+	std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
 	for (auto module : design->modules()) {
 		auto it = module->attributes.find(ID(abc9_lut));
 		if (it == module->attributes.end())
@@ -618,7 +618,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
 		// ABC requires ascending LUT input delays
-		table.emplace_back(GetSize(specify), module->name, std::move(specify));
+		table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
 	}
 	// ABC requires ascending size
 	std::sort(table.begin(), table.end());
@@ -629,15 +629,15 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 	//   (as ABC requires) crop the first entry to do so
 	for (int i = 1; i < std::get<0>(first); i++) {
 		ss << "# $__ABC9_LUT" << i << std::endl;
-		ss << i;
+		ss << i << " " << std::get<2>(first);
 		for (int j = 0; j < i; j++)
-			ss << " " << std::get<2>(first)[j];
+			ss << " " << std::get<3>(first)[j];
 		ss << std::endl;
 	}
 	for (const auto &i : table) {
 		ss << "# " << log_id(std::get<1>(i)) << std::endl;
-		ss << GetSize(std::get<2>(i));
-		for (const auto &j : std::get<2>(i))
+		ss << std::get<0>(i) << " " << std::get<2>(i);
+		for (const auto &j : std::get<3>(i))
 			ss << " " << j;
 		ss << std::endl;
 	}

From ac24a23e31f2da76f8b976cd89b9ec6fadf15374 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:56:00 -0800
Subject: [PATCH 12/46] Create +/abc9_model.v for $__ABC9_{DELAY,FF_}

---
 techlibs/common/Makefile.inc |  1 +
 techlibs/common/abc9_model.v | 10 ++++++++++
 2 files changed, 11 insertions(+)
 create mode 100644 techlibs/common/abc9_model.v

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 42f1068ad..d5e69a241 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -29,3 +29,4 @@ $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
 $(eval $(call add_share_file,share,techlibs/common/mul2dsp.v))
+$(eval $(call add_share_file,share,techlibs/common/abc9_model.v))
diff --git a/techlibs/common/abc9_model.v b/techlibs/common/abc9_model.v
new file mode 100644
index 000000000..c0c5dc2fd
--- /dev/null
+++ b/techlibs/common/abc9_model.v
@@ -0,0 +1,10 @@
+module \$__ABC9_FF_ (input D, output Q);
+endmodule
+
+(* abc9_box *)
+module \$__ABC9_DELAY (input I, output O);
+  parameter DELAY = 0;
+  specify
+    (I => O) = DELAY;
+  endspecify
+endmodule

From 8408c13405bfe561e6a6022e2730ecca18a1464a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:56:30 -0800
Subject: [PATCH 13/46] Update xilinx for ABC9

---
 techlibs/xilinx/abc9_model.v    | 11 -----------
 techlibs/xilinx/cells_sim.v     | 23 +++++++++++++++--------
 techlibs/xilinx/synth_xilinx.cc |  2 +-
 3 files changed, 16 insertions(+), 20 deletions(-)

diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 6beff30ba..8e2a05ceb 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -38,17 +38,6 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
   endspecify
 endmodule
 
-module \$__ABC9_FF_ (input D, output Q);
-endmodule
-
-(* abc9_box *)
-module \$__ABC9_DELAY (input I, output O);
-  parameter DELAY = 0;
-  specify
-    (I => O) = DELAY;
-  endspecify
-endmodule
-
 // Box to emulate async behaviour of FDC*
 (* abc9_box, lib_whitebox *)
 module \$__ABC9_ASYNC0 (input A, S, output Y);
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 1851f1ddc..0be53ef9e 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -227,6 +227,9 @@ module LUT5(output O, input I0, I1, I2, I3, I4);
   endspecify
 endmodule
 
+// This is a placeholder for ABC9 to extract the area/delay
+//   cost of 3-input LUTs and is not intended to be instantiated
+
 (* abc9_lut=5 *)
 module LUT6(output O, input I0, I1, I2, I3, I4, I5);
   parameter [63:0] INIT = 0;
@@ -262,20 +265,24 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
   assign O5 = I0 ? s5_1[1] : s5_1[0];
 endmodule
 
+// This is a placeholder for ABC9 to extract the area/delay
+//   cost of 3-input LUTs and is not intended to be instantiated
 (* abc9_lut=10 *)
 module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
   specify
                                                  // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
-    (I0 => O) = 642 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    (I1 => O) = 631 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    (I2 => O) = 472 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    (I3 => O) = 407 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    (I4 => O) = 238 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    (I5 => O) = 127 + 223 /* to cross MUXF7 */ + 174 /* CMUX */;
-    (I6 => O) = 0 + 296 /* to select MUXF7 */ + 174 /* CMUX */;
+    (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (I1 => O) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (I2 => O) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (I3 => O) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (I4 => O) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
   endspecify
 endmodule
 
+// This is a placeholder for ABC9 to extract the area/delay
+//   cost of 3-input LUTs and is not intended to be instantiated
 (* abc9_lut=20 *)
 module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
   specify
@@ -489,7 +496,7 @@ module FDRE (
     //$setup(D , negedge C &&& CE &&&  IS_C_INVERTED , -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
-    $setup(CE, negedge C &&&  IS_C_INVERTED , 109);
+    $setup(CE, negedge C &&&  IS_C_INVERTED, 109);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(R , posedge C &&& !IS_C_INVERTED, 404);
     $setup(R , negedge C &&&  IS_C_INVERTED, 404);
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index bb3ced8da..8553efd6b 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -619,7 +619,7 @@ struct SynthXilinxPass : public ScriptPass
 				if (dff_mode)
 					techmap_args += " -D DFF_MODE";
 				run("techmap " + techmap_args);
-				run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
+				run("read_verilog -icells -lib -specify +/abc9_model.v +/xilinx/abc9_model.v");
 				std::string abc9_opts;
 				auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
 				if (active_design->scratchpad.count(k))

From a85c55113fbaf62ade66e583942782820fd0e9ff Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:56:52 -0800
Subject: [PATCH 14/46] synth_ecp5: use +/abc9_model.v

---
 techlibs/ecp5/synth_ecp5.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 463ddb5ca..9916fdafb 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -322,7 +322,7 @@ struct SynthEcp5Pass : public ScriptPass
 				run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
+				run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v");
 				if (nowidelut)
 					run("abc9 -maxlut 4 -W 200");
 				else

From fb60d82971a9de5312467c4c192148ab546504dc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 09:58:20 -0800
Subject: [PATCH 15/46] ice40: move over to specify blocks for -abc9

---
 techlibs/ice40/Makefile.inc   |    6 -
 techlibs/ice40/abc9_hx.box    |   17 -
 techlibs/ice40/abc9_hx.lut    |    6 -
 techlibs/ice40/abc9_lp.box    |   17 -
 techlibs/ice40/abc9_lp.lut    |    6 -
 techlibs/ice40/abc9_model.v   |   59 +-
 techlibs/ice40/abc9_u.box     |   17 -
 techlibs/ice40/abc9_u.lut     |    6 -
 techlibs/ice40/cells_sim.v    | 1368 +++++++++++++++++++++++++++++++--
 techlibs/ice40/synth_ice40.cc |    6 +-
 10 files changed, 1344 insertions(+), 164 deletions(-)
 delete mode 100644 techlibs/ice40/abc9_hx.box
 delete mode 100644 techlibs/ice40/abc9_hx.lut
 delete mode 100644 techlibs/ice40/abc9_lp.box
 delete mode 100644 techlibs/ice40/abc9_lp.lut
 delete mode 100644 techlibs/ice40/abc9_u.box
 delete mode 100644 techlibs/ice40/abc9_u.lut

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 31478e80e..b9e504a9d 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -29,12 +29,6 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v))
 $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_model.v))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_hx.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_lp.lut))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.box))
-$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc9_u.lut))
 
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
 $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
diff --git a/techlibs/ice40/abc9_hx.box b/techlibs/ice40/abc9_hx.box
deleted file mode 100644
index 31e743669..000000000
--- a/techlibs/ice40/abc9_hx.box
+++ /dev/null
@@ -1,17 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-
-# NB: Box inputs/outputs must each be in the same order
-#     as their corresponding module definition
-#     (with exceptions detailed below)
-
-# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
-#                                 SB_LUT4+SB_CARRY)
-#   (Exception: carry chain input/output must be the
-#        last input and output and the entire bus has been
-#        moved there overriding the otherwise
-#        alphabetical ordering)
-# name                 ID  w/b ins outs
-$__ICE40_CARRY_WRAPPER 1   1   5   2
-#A  B   I0  I3  CI
-400 379 449 316 316 # O
-259 231 -   -   126 # CO
diff --git a/techlibs/ice40/abc9_hx.lut b/techlibs/ice40/abc9_hx.lut
deleted file mode 100644
index 3b3bb11e2..000000000
--- a/techlibs/ice40/abc9_hx.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
-#       I3  I2  I1  I0
-1   1   316
-2   1   316 379
-3   1   316 379 400
-4   1   316 379 400 449
diff --git a/techlibs/ice40/abc9_lp.box b/techlibs/ice40/abc9_lp.box
deleted file mode 100644
index 71986a67b..000000000
--- a/techlibs/ice40/abc9_lp.box
+++ /dev/null
@@ -1,17 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-
-# NB: Box inputs/outputs must each be in the same order
-#     as their corresponding module definition
-#     (with exceptions detailed below)
-
-# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
-#                                 SB_LUT4+SB_CARRY)
-#   (Exception: carry chain input/output must be the
-#        last input and output and the entire bus has been
-#        moved there overriding the otherwise
-#        alphabetical ordering)
-# name                 ID  w/b ins outs
-$__ICE40_CARRY_WRAPPER 1   1   5   2
-#A  B   I0  I3  CI
-589 558 661 465 465 # O
-675 609 -   -   186 # CO
diff --git a/techlibs/ice40/abc9_lp.lut b/techlibs/ice40/abc9_lp.lut
deleted file mode 100644
index e72f760a2..000000000
--- a/techlibs/ice40/abc9_lp.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
-#       I3  I2  I1  I0
-1   1   465
-2   1   465 558
-3   1   465 558 589
-4   1   465 558 589 661
diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v
index a5e5f4372..abe4134a0 100644
--- a/techlibs/ice40/abc9_model.v
+++ b/techlibs/ice40/abc9_model.v
@@ -1,4 +1,4 @@
-(* abc9_box_id = 1, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module \$__ICE40_CARRY_WRAPPER (
 	(* abc9_carry *)
 	output CO,
@@ -26,4 +26,61 @@ module \$__ICE40_CARRY_WRAPPER (
 		.I3(I3_OR_CI),
 		.O(O)
 	);
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
+		(CI => O) = (126, 105);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
+		(I0 => O) = (449, 386);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
+		(A => CO) = (259, 245);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
+		(A => O) = (400, 379);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
+		(B => CO) = (231, 133);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
+		(B => O) = (379, 351);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
+		(I3 => O) = (316, 288);
+		(CI => O) = (316, 288);
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
+		(CI => O) = (186, 155);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
+		(I0 => O) = (662, 569);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
+		(A => CO) = (382, 362);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
+		(A => O) = (589, 558);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
+		(B => CO) = (341, 196);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
+		(B => O) = (558, 517);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
+		(I3 => O) = (465, 423);
+		(CI => O) = (465, 423);
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
+		(CI => O) = (278, 278);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
+		(I0 => O) = (1245, 1285);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
+		(A => CO) = (675, 662);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
+		(A => O) = (1179, 1232);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
+		(B => CO) = (609, 358);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
+		(B => O) = (1179, 1205);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
+		(I3 => O) = (861, 874);
+		(CI => O) = (861, 874);
+	endspecify
+`endif
 endmodule
diff --git a/techlibs/ice40/abc9_u.box b/techlibs/ice40/abc9_u.box
deleted file mode 100644
index 3d4b93834..000000000
--- a/techlibs/ice40/abc9_u.box
+++ /dev/null
@@ -1,17 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-
-# NB: Box inputs/outputs must each be in the same order
-#     as their corresponding module definition
-#     (with exceptions detailed below)
-
-# Box 1 : $__ICE40_CARRY_WRAPPER (private cell used to preserve
-#                                 SB_LUT4+SB_CARRY)
-#   (Exception: carry chain input/output must be the
-#        last input and output and the entire bus has been
-#        moved there overriding the otherwise
-#        alphabetical ordering)
-# name                 ID  w/b ins outs
-$__ICE40_CARRY_WRAPPER 1   1   5   2
-#A   B    I0   I3  CI
-1231 1205 1285 874 874 # O
-675  609  -    -   278 # CO
diff --git a/techlibs/ice40/abc9_u.lut b/techlibs/ice40/abc9_u.lut
deleted file mode 100644
index 1e4fcadb6..000000000
--- a/techlibs/ice40/abc9_u.lut
+++ /dev/null
@@ -1,6 +0,0 @@
-# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
-#       I3  I2  I1  I0
-1   1   874
-2   1   874 1205
-3   1   874 1205 1231
-4   1   874 1205 1231 1285
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 50eab5dde..e20e2e657 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -2,10 +2,6 @@
 `define SB_DFF_REG reg Q = 0
 // `define SB_DFF_REG reg Q
 
-`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif
-`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif
-`define ABC9_ARRIVAL_U(TIME)  `ifdef ICE40_U (* abc9_arrival=TIME *) `endif
-
 // SiliconBlue IO Cells
 
 module SB_IO (
@@ -167,13 +163,49 @@ endmodule
 
 // SiliconBlue Logic Cells
 
-(* lib_whitebox *)
+(* abc9_lut=1, lib_whitebox *)
 module SB_LUT4 (output O, input I0, I1, I2, I3);
 	parameter [15:0] LUT_INIT = 0;
 	wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
 	wire [3:0] s2 = I2 ?       s3[ 7:4] :       s3[3:0];
 	wire [1:0] s1 = I1 ?       s2[ 3:2] :       s2[1:0];
 	assign O = I0 ? s1[1] : s1[0];
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
+		(I0 => O) = (449, 386);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L83
+		(I1 => O) = (400, 379);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L86
+		(I2 => O) = (379, 351);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L88
+		(I3 => O) = (316, 288);
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
+		(I0 => O) = (662, 569);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L83
+		(I1 => O) = (589, 558);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L86
+		(I2 => O) = (558, 517);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L88
+		(I3 => O) = (465, 423);
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
+		(I0 => O) = (1245, 1285);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L95
+		(I1 => O) = (1179, 1232);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L98
+		(I2 => O) = (1179, 1205);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L100
+		(I3 => O) = (861, 874);
+	endspecify
+`endif
 endmodule
 
 (* lib_whitebox *)
@@ -181,39 +213,86 @@ module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
 endmodule
 
-// Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
-//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
-//                 https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
-
 // Positive Edge SiliconBlue FF Cells
 
 module SB_DFF (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
 	always @(posedge C)
 		Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		(posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		(posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		(posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFE (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
 	always @(posedge C)
 		if (E)
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFSR (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -222,12 +301,45 @@ module SB_DFFSR (
 			Q <= 0;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if ( R) (posedge C => (Q : 1'b0)) = 540;
+		if (!R) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if ( R) (posedge C => (Q : 1'b0)) = 796;
+		if (!R) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if ( R) (posedge C => (Q : 1'b0)) = 1391;
+		if (!R) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFR (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -236,12 +348,48 @@ module SB_DFFR (
 			Q <= 0;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (!R) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (!R) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge R => (Q : 1'b0)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (!R) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFSS (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -250,12 +398,45 @@ module SB_DFFSS (
 			Q <= 1;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if ( S) (posedge C => (Q : 1'b1)) = 540;
+		if (!S) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if ( S) (posedge C => (Q : 1'b1)) = 796;
+		if (!S) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if ( S) (posedge C => (Q : 1'b1)) = 1391;
+		if (!S) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFS (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -264,12 +445,48 @@ module SB_DFFS (
 			Q <= 1;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (!S) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (!S) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge S => (Q : 1'b1)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (!S) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFESR (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -280,12 +497,51 @@ module SB_DFFESR (
 			else
 				Q <= D;
 		end
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C &&& E && !R, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, posedge C &&& E, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E &&  R) (posedge C => (Q : 1'b0)) = 540;
+		if (E && !R) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C &&& E && !R, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, posedge C &&& E, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E &&  R) (posedge C => (Q : 1'b0)) = 796;
+		if (E && !R) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, posedge C &&& E, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E &&  R) (posedge C => (Q : 1'b0)) = 1391;
+		if (E && !R) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFER (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -294,12 +550,54 @@ module SB_DFFER (
 			Q <= 0;
 		else if (E)
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E && !R) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E && !R) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge R => (Q : 1'b0)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E && !R) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFESS (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -310,12 +608,51 @@ module SB_DFFESS (
 			else
 				Q <= D;
 		end
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C &&& E && !S, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, posedge C &&& E, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E &&  S) (posedge C => (Q : 1'b1)) = 540;
+		if (E && !S) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C &&& E && !S, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, posedge C &&& E, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E &&  S) (posedge C => (Q : 1'b1)) = 796;
+		if (E && !S) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, posedge C &&& E, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E &&  S) (posedge C => (Q : 1'b1)) = 1391;
+		if (E && !S) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFES (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -324,37 +661,133 @@ module SB_DFFES (
 			Q <= 1;
 		else if (E)
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, posedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E && !S) (posedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, posedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E && !S) (posedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, posedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge S => (Q : 1'b1)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E && !S) (posedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 // Negative Edge SiliconBlue FF Cells
 
 module SB_DFFN (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, D
 );
 	always @(negedge C)
 		Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		(negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		(negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		(negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNE (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, D
 );
 	always @(negedge C)
 		if (E)
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNSR (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -363,12 +796,45 @@ module SB_DFFNSR (
 			Q <= 0;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if ( R) (negedge C => (Q : 1'b0)) = 540;
+		if (!R) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if ( R) (negedge C => (Q : 1'b0)) = 796;
+		if (!R) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if ( R) (negedge C => (Q : 1'b0)) = 1391;
+		if (!R) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNR (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, R, D
 );
@@ -377,12 +843,48 @@ module SB_DFFNR (
 			Q <= 0;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (!R) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (!R) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge R => (Q : 1'b0)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (!R) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNSS (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -391,12 +893,45 @@ module SB_DFFNSS (
 			Q <= 1;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if ( S) (negedge C => (Q : 1'b1)) = 540;
+		if (!S) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if ( S) (negedge C => (Q : 1'b1)) = 796;
+		if (!S) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if ( S) (negedge C => (Q : 1'b1)) = 1391;
+		if (!S) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNS (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, S, D
 );
@@ -405,12 +940,48 @@ module SB_DFFNS (
 			Q <= 1;
 		else
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (!S) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (!S) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge S => (Q : 1'b1)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (!S) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNESR (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -421,12 +992,51 @@ module SB_DFFNESR (
 			else
 				Q <= D;
 		end
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C &&& E && !R, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, negedge C &&& E, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E &&  R) (negedge C => (Q : 1'b0)) = 540;
+		if (E && !R) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C &&& E && !R, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, negedge C &&& E, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E &&  R) (negedge C => (Q : 1'b0)) = 796;
+		if (E && !R) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, negedge C &&& E, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E &&  R) (negedge C => (Q : 1'b0)) = 1391;
+		if (E && !R) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNER (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, R, D
 );
@@ -435,12 +1045,54 @@ module SB_DFFNER (
 			Q <= 0;
 		else if (E)
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(R, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E && !R) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(R, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge R => (Q : 1'b0)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E && !R) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(R, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge R => (Q : 1'b0)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E && !R) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNESS (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -451,12 +1103,51 @@ module SB_DFFNESS (
 			else
 				Q <= D;
 		end
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C &&& E && !S, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, negedge C &&& E, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E &&  S) (negedge C => (Q : 1'b1)) = 540;
+		if (E && !S) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C &&& E && !S, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, negedge C &&& E, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E &&  S) (negedge C => (Q : 1'b1)) = 796;
+		if (E && !S) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, negedge C &&& E, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E &&  S) (negedge C => (Q : 1'b1)) = 1391;
+		if (E && !S) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 module SB_DFFNES (
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output `SB_DFF_REG,
 	input C, E, S, D
 );
@@ -465,14 +1156,56 @@ module SB_DFFNES (
 			Q <= 1;
 		else if (E)
 			Q <= D;
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+		$setup(D, negedge C &&& E, 470 - 449);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		$setup(S, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 599;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+		if (E && !S) (negedge C => (Q : D)) = 540;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		$setup(D, negedge C &&& E, 693 - 662);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+		$setup(S, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
+		(posedge S => (Q : 1'b1)) = 883;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+		if (E && !S) (negedge C => (Q : D)) = 796;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+		$setup(E, negedge C, 0);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+		$setup(S, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
+		(posedge S => (Q : 1'b1)) = 1589;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+		if (E && !S) (negedge C => (Q : D)) = 1391;
+	endspecify
+`endif
 endmodule
 
 // SiliconBlue RAM Cells
 
 module SB_RAM40_4K (
-	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -638,12 +1371,75 @@ module SB_RAM40_4K (
 		end
 	end
 `endif
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
+		$setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
+		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
+		$setup(RCLKE, posedge RCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
+		$setup(RE, posedge RCLK, 98);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
+		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
+		$setup(WCLKE, posedge WCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
+		$setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
+		$setup(WE, posedge WCLK, 133);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+		(posedge RCLK => (RDATA : 16'bx)) = 2146;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
+		$setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
+		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
+		$setup(RCLKE, posedge RCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
+		$setup(RE, posedge RCLK, 145);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
+		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
+		$setup(WCLKE, posedge WCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
+		$setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
+		$setup(WE, posedge WCLK, 196);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+		(posedge RCLK => (RDATA : 16'bx)) = 3163;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
+		$setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
+		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
+		$setup(RCLKE, posedge RCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
+		$setup(RE, posedge RCLK, 185);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
+		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
+		$setup(WCLKE, posedge WCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
+		$setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
+		$setup(WE, posedge WCLK, 252);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+		(posedge RCLK => (RDATA : 16'bx)) = 1179;
+	endspecify
+`endif
 endmodule
 
 module SB_RAM40_4KNR (
-	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -706,12 +1502,75 @@ module SB_RAM40_4KNR (
 		.MASK (MASK ),
 		.WDATA(WDATA)
 	);
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
+		$setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
+		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
+		$setup(RCLKE, negedge RCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
+		$setup(RE, negedge RCLK, 98);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
+		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
+		$setup(WCLKE, posedge WCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
+		$setup(WDATA, posedge WCLK &&& WE && WCLKE, 161);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
+		$setup(WE, posedge WCLK, 133);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+		(negedge RCLK => (RDATA : 16'bx)) = 2146;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
+		$setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
+		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 300);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
+		$setup(RCLKE, negedge RCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
+		$setup(RE, negedge RCLK, 145);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
+		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
+		$setup(WCLKE, posedge WCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
+		$setup(WDATA, posedge WCLK &&& WE && WCLKE, 238);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
+		$setup(WE, posedge WCLK, 196);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+		(negedge RCLK => (RDATA : 16'bx)) = 3163;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
+		$setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
+		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 384);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
+		$setup(RCLKE, negedge RCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
+		$setup(RE, negedge RCLK, 185);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
+		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
+		$setup(WCLKE, posedge WCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
+		$setup(WDATA, posedge WCLK &&& WE && WCLKE, 305);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
+		$setup(WE, posedge WCLK, 252);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+		(negedge RCLK => (RDATA : 16'bx)) = 1179;
+	endspecify
+`endif
 endmodule
 
 module SB_RAM40_4KNW (
-	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLK, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -774,12 +1633,75 @@ module SB_RAM40_4KNW (
 		.MASK (MASK ),
 		.WDATA(WDATA)
 	);
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
+		$setup(MASK, negedge WCLK &&& WE && WCLKE, 274);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
+		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
+		$setup(RCLKE, posedge RCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
+		$setup(RE, posedge RCLK, 98);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
+		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 224);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
+		$setup(WCLKE, negedge WCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
+		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 161);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
+		$setup(WE, negedge WCLK, 133);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+		(posedge RCLK => (RDATA : 16'bx)) = 2146;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
+		$setup(MASK, negedge WCLK &&& WE && WCLKE, 403);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
+		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
+		$setup(RCLKE, posedge RCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
+		$setup(RE, posedge RCLK, 145);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
+		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 331);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
+		$setup(WCLKE, negedge WCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
+		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 238);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
+		$setup(WE, negedge WCLK, 196);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+		(posedge RCLK => (RDATA : 16'bx)) = 3163;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
+		$setup(MASK, negedge WCLK &&& WE && WCLKE, 517);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
+		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
+		$setup(RCLKE, posedge RCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
+		$setup(RE, posedge RCLK, 185);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
+		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 424);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
+		$setup(WCLKE, negedge WCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
+		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 305);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
+		$setup(WE, negedge WCLK, 252);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+		(posedge RCLK => (RDATA : 16'bx)) = 1179;
+	endspecify
+`endif
 endmodule
 
 module SB_RAM40_4KNRNW (
-	`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-	`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-	`ABC9_ARRIVAL_U(1179)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 	output [15:0] RDATA,
 	input         RCLKN, RCLKE, RE,
 	input  [10:0] RADDR,
@@ -842,6 +1764,72 @@ module SB_RAM40_4KNRNW (
 		.MASK (MASK ),
 		.WDATA(WDATA)
 	);
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
+		$setup(MASK, negedge WCLK &&& WE && WCLKE, 274);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
+		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
+		$setup(RCLKE, negedge RCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
+		$setup(RE, negedge RCLK, 98);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
+		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 224);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
+		$setup(WCLKE, negedge WCLK, 267);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
+		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 161);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
+		$setup(WE, negedge WCLK, 133);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
+		(negedge RCLK => (RDATA : 16'bx)) = 2146;
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
+		$setup(MASK, negedge WCLK &&& WE && WCLKE, 403);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
+		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 300);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
+		$setup(RCLKE, negedge RCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
+		$setup(RE, negedge RCLK, 145);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
+		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 331);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
+		$setup(WCLKE, negedge WCLK, 393);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
+		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 238);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
+		$setup(WE, negedge WCLK, 196);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
+		(negedge RCLK => (RDATA : 16'bx)) = 3163;
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
+		$setup(MASK, negedge WCLK &&& WE && WCLKE, 517);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
+		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 384);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
+		$setup(RCLKE, negedge RCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
+		$setup(RE, negedge RCLK, 185);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
+		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 424);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
+		$setup(WCLKE, negedge WCLK, 503);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
+		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 305);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
+		$setup(WE, negedge WCLK, 252);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
+		(negedge RCLK => (RDATA : 16'bx)) = 1179;
+	endspecify
+`endif
 endmodule
 
 // Packed IceStorm Logic Cells
@@ -849,9 +1837,6 @@ endmodule
 module ICESTORM_LC (
 	input I0, I1, I2, I3, CIN, CLK, CEN, SR,
 	output LO,
-	`ABC9_ARRIVAL_HX(540)
-	`ABC9_ARRIVAL_LP(796)
-	`ABC9_ARRIVAL_U(1391)
 	output O,
 	output COUT
 );
@@ -941,6 +1926,198 @@ specify
 	$setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0);
 endspecify
 `endif
+`ifdef ICE40_HX
+specify
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L79
+	(CIN => COUT) = (101:112:126, 85:94:105);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
+	(I0 => O) = (361:399:449, 310:343:386);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L81
+	(I0 => LO) = (293:324:365, 310:343:386);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L82
+	(I1 => COUT) = (209:231:259, 197:218:245);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L83
+	(I1 => O) = (321:355:400, 304:337:379);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L84
+	(I1 => LO) = (259:287:323, 304:337:379);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L85
+	(I2 => COUT) = (186:206:231, 107:118:133);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L86
+	(I2 => O) = (304:337:379, 282:312:351);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L87
+	(I2 => LO) = (254:281:316, 231:256:288);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L88
+	(I3 => O) = (254:281:316, 231:256:288);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L89
+	(I3 => LO) = (214:237:267, 220:243:274);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
+	(posedge CLK => (O : 1'bx)) = (434:480:540, 434:480:540);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91-L92
+	(SR => O) = (482:535:599, 482:533:599);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
+	$setuphold(posedge CLK, posedge I0, 378:418:470, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L68
+	$setuphold(posedge CLK, negedge I0, 321:355:400, 0:0:0);
+	$setuphold(negedge CLK, posedge I0, 378:418:470, 0:0:0);
+	$setuphold(negedge CLK, negedge I0, 321:355:400, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L75
+	$setuphold(posedge CLK, posedge I1, 321:355:400, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L69
+	$setuphold(posedge CLK, negedge I1, 304:337:379, 0:0:0);
+	$setuphold(negedge CLK, posedge I1, 321:355:400, 0:0:0);
+	$setuphold(negedge CLK, negedge I1, 304:337:379, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L76
+	$setuphold(posedge CLK, posedge I2, 299:330:372, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L70
+	$setuphold(posedge CLK, negedge I2, 259:287:323, 0:0:0);
+	$setuphold(negedge CLK, posedge I2, 299:330:372, 0:0:0);
+	$setuphold(negedge CLK, negedge I2, 259:287:323, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L77
+	$setuphold(posedge CLK, posedge I3, 220:243:274, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L71
+	$setuphold(posedge CLK, negedge I3, 175:183:217, 0:0:0);
+	$setuphold(negedge CLK, posedge I3, 220:243:274, 0:0:0);
+	$setuphold(negedge CLK, negedge I3, 175:183:217, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+	$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L67
+	$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
+	$setuphold(posedge CLK, posedge SR, 163:181:203, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L72
+	$setuphold(posedge CLK, negedge SR, 113:125:140, 0:0:0);
+	$setuphold(negedge CLK, posedge SR, 163:181:203, 0:0:0);
+	$setuphold(negedge CLK, negedge SR, 113:125:140, 0:0:0);
+endspecify
+`endif
+`ifdef ICE40_LX
+specify
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L79
+	(CIN => COUT) = (118:153:186, 98:128:155);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
+	(I0 => O) = (419:545:662, 360:468:569);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L81
+	(I0 => LO) = (340:442:538, 360:468:569);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L82
+	(I1 => COUT) = (242:315:382, 229:298:362);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L83
+	(I1 => O) = (372:485:589, 353:459:558);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L84
+	(I1 => LO) = (301:391:475, 353:459:558);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L85
+	(I2 => COUT) = (216:281:341, 124:162:196);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
+	(I2 => O) = (353:459:558, 327:425:517);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L87
+	(I2 => LO) = (288:374:455, 321:417:507);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L88
+	(I3 => O) = (294:383:465, 268:349:424);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L89
+	(I3 => LO) = (249:323:393, 255:332:403);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
+	(posedge CLK => O) = (504:655:796, 504:655:796);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91-L92
+	(SR => O) = (559:726:883, 559:726:883);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
+	$setuphold(posedge CLK, posedge I0, 438:570:693, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L68
+	$setuphold(posedge CLK, negedge I0, 373:485:589, 0:0:0);
+	$setuphold(negedge CLK, posedge I0, 438:570:693, 0:0:0);
+	$setuphold(negedge CLK, negedge I0, 373:485:589, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L75
+	$setuphold(posedge CLK, posedge I1, 373:485:589, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L69
+	$setuphold(posedge CLK, negedge I1, 353:459:558, 0:0:0);
+	$setuphold(negedge CLK, posedge I1, 373:485:589, 0:0:0);
+	$setuphold(negedge CLK, negedge I1, 353:459:558, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L76
+	$setuphold(posedge CLK, posedge I2, 347:451:548, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L70
+	$setuphold(posedge CLK, negedge I2, 301:391:475, 0:0:0);
+	$setuphold(negedge CLK, posedge I2, 347:451:548, 0:0:0);
+	$setuphold(negedge CLK, negedge I2, 301:391:475, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L77
+	$setuphold(posedge CLK, posedge I3, 255:332:403, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L71
+	$setuphold(posedge CLK, negedge I3, 203:264:320, 0:0:0);
+	$setuphold(negedge CLK, posedge I3, 255:332:403, 0:0:0);
+	$setuphold(negedge CLK, negedge I3, 203:264:320, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
+	$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L67
+	$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
+	$setuphold(posedge CLK, posedge SR, 190:247:300, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L72
+	$setuphold(posedge CLK, negedge SR, 131:170:207, 0:0:0);
+	$setuphold(negedge CLK, posedge SR, 190:247:300, 0:0:0);
+	$setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
+endspecify
+`endif
+`ifdef ICE40_U
+specify
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L91
+	(CIN => COUT) = (103:181:278, 103:181:278);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L92
+	(I0 => O) = (462:808:1255, 477:834:1285);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L93
+	(I0 => LO) = (315:550:848, 334:585:901);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L94
+	(I1 => COUT) = (251:438:675, 246:430:662);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L95
+	(I1 => O) = (438:765:1179, 457:799:1232);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L96
+	(I1 => LO) = (275:481:742, 329:576:887);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L97
+	(I2 => COUT) = (226:395:609, 133:232:358);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L98
+	(I2 => O) = (438:765:1179, 447:782:1205);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L99
+	(I2 => LO) = (261:456:702, 290:507:781);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L100
+	(I3 => O) = (320:559:861, 226:370:874);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L101
+	(I3 => LO) = (216:378:583, 226:395:609);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
+	(posedge CLK => O) = (516:903:1391, 516:903:1391);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103-104
+	(SR => O) = (420:734:1131, 590:1032:1589);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
+	$setuphold(posedge CLK, posedge I0, 457:799:1232, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L80
+	$setuphold(posedge CLK, negedge I0, 393:688:1060, 0:0:0);
+	$setuphold(negedge CLK, posedge I0, 457:799:1232, 0:0:0);
+	$setuphold(negedge CLK, negedge I0, 393:688:1060, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L87
+	$setuphold(posedge CLK, posedge I1, 393:688:1060, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L81
+	$setuphold(posedge CLK, negedge I1, 373:653:1007, 0:0:0);
+	$setuphold(negedge CLK, posedge I1, 393:688:1060, 0:0:0);
+	$setuphold(negedge CLK, negedge I1, 373:653:1007, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L88
+	$setuphold(posedge CLK, posedge I2, 364:636:980, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L82
+	$setuphold(posedge CLK, negedge I2, 320:559:861, 0:0:0);
+	$setuphold(negedge CLK, posedge I2, 364:636:980, 0:0:0);
+	$setuphold(negedge CLK, negedge I2, 320:559:861, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L89
+	$setuphold(posedge CLK, posedge I3, 279:473:728, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L83
+	$setuphold(posedge CLK, negedge I3, 216:378:583, 0:0:0);
+	$setuphold(negedge CLK, posedge I3, 279:473:728, 0:0:0);
+	$setuphold(negedge CLK, negedge I3, 216:378:583, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L85
+	$setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L79
+	$setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
+	$setuphold(posedge CLK, posedge SR, 197:344:530, 0:0:0);
+	// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L84
+	$setuphold(posedge CLK, negedge SR, 143:249:384, 0:0:0);
+	$setuphold(negedge CLK, posedge SR, 197:344:530, 0:0:0);
+	$setuphold(negedge CLK, negedge SR, 131:170:207, 0:0:0);
+endspecify
+`endif
 endmodule
 
 // SiliconBlue PLL Cells
@@ -1126,7 +2303,6 @@ module SB_SPRAM256KA (
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
 	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
-	`ABC9_ARRIVAL_U(1821)  // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207
 	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
@@ -1158,6 +2334,28 @@ module SB_SPRAM256KA (
 	end
 `endif
 `endif
+`ifdef ICE40_U
+	specify
+		https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13169-L13182
+		$setup(posedge ADDRESS, posedge CLOCK, 268);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13183
+		$setup(CHIPSELECT, posedge CLOCK, 404);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13184-L13199
+		$setup(DATAIN, posedge CLOCK, 143);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13200-L13203
+		$setup(MASKWREN, posedge CLOCK, 143);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
+		//$setup(negedge SLEEP, posedge CLOCK, 41505);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13167
+		//$setup(negedge STANDBY, posedge CLOCK, 1715);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206
+		$setup(WREN, posedge CLK, 289);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222
+		(posedge RCLK => (DATAOUT : 16'bx)) = 1821;
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238
+		(posedge SLEEP => (DATAOUT : 16'b0)) = 1099;
+	endspecify
+`endif
 endmodule
 
 (* blackbox *)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index fdb203dcb..7466ef1c2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
 				define = "-D ICE40_U";
 			else
 				define = "-D ICE40_HX";
-			run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
+			run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
 		}
@@ -352,7 +352,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc9) {
-					run("read_verilog -icells -lib +/ice40/abc9_model.v");
+					run("read_verilog -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
 					int wire_delay;
 					if (device_opt == "lp")
 						wire_delay = 400;
@@ -360,7 +360,7 @@ struct SynthIce40Pass : public ScriptPass
 						wire_delay = 750;
 					else
 						wire_delay = 250;
-					run(stringf("abc9 -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()));
+					run(stringf("abc9 -W %d", wire_delay, device_opt.c_str(), device_opt.c_str()));
 				}
 				else
 					run("abc -dress -lut 4", "(skip if -noabc)");

From 7c92b6852f3bcc962e72bb787ac51e3f4324a4fb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 10:30:29 -0800
Subject: [PATCH 16/46] abc9_ops: sort LUT delays to be ascending

---
 passes/techmap/abc9_ops.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 61a3880b7..e1ab70f11 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -617,7 +617,8 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		}
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
-		// ABC requires ascending LUT input delays
+		// ABC requires non-decreasing LUT input delays
+		std::sort(specify.begin(), specify.end());
 		table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
 	}
 	// ABC requires ascending size
@@ -777,6 +778,8 @@ void prep_box(RTLIL::Design *design)
 				log_assert(GetSize(src) == GetSize(dst));
 				for (auto i = 0; i < GetSize(src); i++) {
 					auto r = table.insert(std::make_pair(src[i],dst[i]));
+					if (!r.second)
+						log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(src[i]), log_signal(dst[i]));
 					log_assert(r.second);
 					r.first->second = std::to_string(max);
 				}

From a76520112d6a7ab894a3e85b7e32def6b4ff5491 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 10:30:56 -0800
Subject: [PATCH 17/46] ice40: specify fixes

---
 techlibs/ice40/abc9_model.v   |   6 +-
 techlibs/ice40/cells_sim.v    | 108 +++++++++++++++++-----------------
 techlibs/ice40/synth_ice40.cc |  18 +++---
 3 files changed, 66 insertions(+), 66 deletions(-)

diff --git a/techlibs/ice40/abc9_model.v b/techlibs/ice40/abc9_model.v
index abe4134a0..84923d381 100644
--- a/techlibs/ice40/abc9_model.v
+++ b/techlibs/ice40/abc9_model.v
@@ -29,7 +29,7 @@ module \$__ICE40_CARRY_WRAPPER (
 `ifdef ICE40_HX
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
-		(CI => O) = (126, 105);
+		(CI => CO) = (126, 105);
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L80
 		(I0 => O) = (449, 386);
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
@@ -48,7 +48,7 @@ module \$__ICE40_CARRY_WRAPPER (
 `ifdef ICE40_LP
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
-		(CI => O) = (186, 155);
+		(CI => CO) = (186, 155);
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L80
 		(I0 => O) = (662, 569);
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
@@ -67,7 +67,7 @@ module \$__ICE40_CARRY_WRAPPER (
 `ifdef ICE40_U
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
-		(CI => O) = (278, 278);
+		(CI => CO) = (278, 278);
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L92
 		(I0 => O) = (1245, 1285);
 		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e20e2e657..380935569 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -306,7 +306,7 @@ module SB_DFFSR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
 		$setup(D, posedge C, 470 - 449);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
 		$setup(R, posedge C, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 		if ( R) (posedge C => (Q : 1'b0)) = 540;
@@ -353,8 +353,8 @@ module SB_DFFR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
 		$setup(D, posedge C, 470 - 449);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(R, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(negedge R, posedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -366,8 +366,8 @@ module SB_DFFR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		$setup(D, posedge C, 693 - 662);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(R, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(negedge R, posedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -379,8 +379,8 @@ module SB_DFFR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(R, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge R, posedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge R => (Q : 1'b0)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -403,7 +403,7 @@ module SB_DFFSS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
 		$setup(D, posedge C, 470 - 449);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
 		$setup(S, posedge C, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 		if ( S) (posedge C => (Q : 1'b1)) = 540;
@@ -450,8 +450,8 @@ module SB_DFFS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
 		$setup(D, posedge C, 470 - 449);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(S, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(negedge S, posedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -463,8 +463,8 @@ module SB_DFFS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		$setup(D, posedge C, 693 - 662);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(S, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(negedge S, posedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -476,8 +476,8 @@ module SB_DFFS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		//$setup(D, posedge C, 1232 - 1285); // Negative times not currently supported
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(S, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge S, posedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge S => (Q : 1'b1)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -504,7 +504,7 @@ module SB_DFFESR (
 		$setup(D, posedge C &&& E && !R, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
 		$setup(R, posedge C &&& E, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 		if (E &&  R) (posedge C => (Q : 1'b0)) = 540;
@@ -557,8 +557,8 @@ module SB_DFFER (
 		$setup(D, posedge C &&& E, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(R, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(negedge R, posedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -572,8 +572,8 @@ module SB_DFFER (
 		$setup(D, posedge C &&& E, 693 - 662);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(R, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(negedge R, posedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -587,8 +587,8 @@ module SB_DFFER (
 		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(R, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge R, posedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge R => (Q : 1'b0)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -615,7 +615,7 @@ module SB_DFFESS (
 		$setup(D, posedge C &&& E && !S, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
 		$setup(S, posedge C &&& E, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 		if (E &&  S) (posedge C => (Q : 1'b1)) = 540;
@@ -668,8 +668,8 @@ module SB_DFFES (
 		$setup(D, posedge C &&& E, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(S, posedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(posedge S, posedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -683,8 +683,8 @@ module SB_DFFES (
 		$setup(D, posedge C &&& E, 693 - 662);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(S, posedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(posedge S, posedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -698,8 +698,8 @@ module SB_DFFES (
 		//$setup(D, posedge C &&& E, 1232 - 1285); // Negative times not currently supported
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
 		$setup(E, posedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(S, posedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(posedge S, posedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge S => (Q : 1'b1)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -848,8 +848,8 @@ module SB_DFFNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
 		$setup(D, negedge C, 470 - 449);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(R, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(negedge R, negedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -861,8 +861,8 @@ module SB_DFFNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		$setup(D, negedge C, 693 - 662);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(R, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(negedge R, negedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -874,8 +874,8 @@ module SB_DFFNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		//$setup(D, negedge C, 1232 - 1285); // Negative times not currently supported
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(R, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge R, negedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge R => (Q : 1'b0)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -945,8 +945,8 @@ module SB_DFFNS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L80
 		$setup(D, negedge C &&& E, 470 - 449);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(S, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(negedge S, negedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -958,8 +958,8 @@ module SB_DFFNS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L74
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		$setup(D, negedge C &&& E, 693 - 662);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(S, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(negedge S, negedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -971,8 +971,8 @@ module SB_DFFNS (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L86
 		//   minus https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L80
 		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(S, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge S, negedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge S => (Q : 1'b1)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -999,7 +999,7 @@ module SB_DFFNESR (
 		$setup(D, negedge C &&& E && !R, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
 		$setup(R, negedge C &&& E, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 		if (E &&  R) (negedge C => (Q : 1'b0)) = 540;
@@ -1052,8 +1052,8 @@ module SB_DFFNER (
 		$setup(D, negedge C &&& E, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(R, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(R, negedge C, 2160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -1067,8 +1067,8 @@ module SB_DFFNER (
 		$setup(D, negedge C &&& E, 693 - 662);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(R, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(R, negedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge R => (Q : 1'b0)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -1082,8 +1082,8 @@ module SB_DFFNER (
 		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(R, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge R, negedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge R => (Q : 1'b0)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
@@ -1110,7 +1110,7 @@ module SB_DFFNESS (
 		$setup(D, negedge C &&& E && !S, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L78
 		$setup(S, negedge C &&& E, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
 		if (E &&  S) (negedge C => (Q : 1'b1)) = 540;
@@ -1163,8 +1163,8 @@ module SB_DFFNES (
 		$setup(D, negedge C &&& E, 470 - 449);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L73
-		$setup(S, negedge C, 203);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L63
+		$setup(negedge S, negedge C, 160);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 599;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90
@@ -1178,8 +1178,8 @@ module SB_DFFNES (
 		$setup(D, negedge C &&& E, 693 - 662);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L73
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L78
-		$setup(S, negedge C, 299);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L63
+		$setup(negedge S, negedge C, 235);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L91
 		(posedge S => (Q : 1'b1)) = 883;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90
@@ -1193,8 +1193,8 @@ module SB_DFFNES (
 		//$setup(D, negedge C &&& E, 1232 - 1285); // Negative times not currently supported
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L86
 		$setup(E, negedge C, 0);
-		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L90
-		$setup(S, negedge C, 530);
+		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L75
+		$setup(negedge S, negedge C, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L103
 		(posedge S => (Q : 1'b1)) = 1589;
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7466ef1c2..f9c5a750b 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -236,15 +236,15 @@ struct SynthIce40Pass : public ScriptPass
 
 	void script() YS_OVERRIDE
 	{
+		std::string define;
+		if (device_opt == "lp")
+			define = "-D ICE40_LP";
+		else if (device_opt == "u")
+			define = "-D ICE40_U";
+		else
+			define = "-D ICE40_HX";
 		if (check_label("begin"))
 		{
-			std::string define;
-			if (device_opt == "lp")
-				define = "-D ICE40_LP";
-			else if (device_opt == "u")
-				define = "-D ICE40_U";
-			else
-				define = "-D ICE40_HX";
 			run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 			run("proc");
@@ -352,7 +352,7 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc9) {
-					run("read_verilog -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
+					run("read_verilog " + define + " -icells -lib -specify +/abc9_model.v +/ice40/abc9_model.v");
 					int wire_delay;
 					if (device_opt == "lp")
 						wire_delay = 400;
@@ -360,7 +360,7 @@ struct SynthIce40Pass : public ScriptPass
 						wire_delay = 750;
 					else
 						wire_delay = 250;
-					run(stringf("abc9 -W %d", wire_delay, device_opt.c_str(), device_opt.c_str()));
+					run(stringf("abc9 -W %d", wire_delay));
 				}
 				else
 					run("abc -dress -lut 4", "(skip if -noabc)");

From e22fee6cdd905535c50c9b6d96a89e994944ea2c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 11:15:59 -0800
Subject: [PATCH 18/46] abc9_ops: ignore (* abc9_flop *) if not '-dff'

---
 backends/aiger/xaiger.cc    |  86 +++++++++++++-----------
 passes/techmap/abc9.cc      |   8 +--
 passes/techmap/abc9_ops.cc  | 128 ++++++++++++++++++------------------
 techlibs/xilinx/cells_sim.v |   8 ++-
 4 files changed, 120 insertions(+), 110 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index c996b0776..16d48a932 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -186,7 +186,6 @@ struct XAigerWriter
 
 		dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache;
 		for (auto cell : module->cells()) {
-			RTLIL::Module* inst_module = module->design->module(cell->type);
 			if (!cell->has_keep_attr()) {
 				if (cell->type == "$_NOT_")
 				{
@@ -229,9 +228,16 @@ struct XAigerWriter
 
 				if (cell->type.in("$specify2", "$specify3", "$specrule"))
 					continue;
+			}
 
-				if (inst_module) {
-					bool abc9_flop = false;
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			if (inst_module) {
+				IdString derived_type = inst_module->derive(module->design, cell->parameters);
+				inst_module = module->design->module(derived_type);
+				log_assert(inst_module);
+
+				bool abc9_flop = false;
+				if (!cell->has_keep_attr()) {
 					auto it = cell->attributes.find("\\abc9_box_seq");
 					if (it != cell->attributes.end()) {
 						int abc9_box_seq = it->second.as_int();
@@ -244,50 +250,50 @@ struct XAigerWriter
 						if (!abc9_flop)
 							continue;
 					}
+				}
 
-					auto &cell_arrivals = arrivals_cache[cell->type];
-					for (const auto &conn : cell->connections()) {
-						auto port_wire = inst_module->wire(conn.first);
-						if (!port_wire->port_output)
+				auto &cell_arrivals = arrivals_cache[derived_type];
+				for (const auto &conn : cell->connections()) {
+					auto port_wire = inst_module->wire(conn.first);
+					if (!port_wire->port_output)
+						continue;
+
+					auto r = cell_arrivals.insert(conn.first);
+					auto &arrivals = r.first->second;
+					if (r.second) {
+						auto it = port_wire->attributes.find("\\abc9_arrival");
+						if (it == port_wire->attributes.end())
 							continue;
-
-						auto r = cell_arrivals.insert(conn.first);
-						auto &arrivals = r.first->second;
-						if (r.second) {
-							auto it = port_wire->attributes.find("\\abc9_arrival");
-							if (it == port_wire->attributes.end())
-								continue;
-							if (it->second.flags == 0)
-								arrivals.emplace_back(it->second.as_int());
-							else
-								for (const auto &tok : split_tokens(it->second.decode_string()))
-									arrivals.push_back(atoi(tok.c_str()));
-						}
-
-						if (arrivals.empty())
-							continue;
-
-						if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
-							log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
-									GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
-
-						auto jt = arrivals.begin();
-#ifndef NDEBUG
-						if (ys_debug(1)) {
-							static std::set<std::pair<IdString,IdString>> seen;
-							if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
-						}
-#endif
-						for (auto bit : sigmap(conn.second)) {
-							arrival_times[bit] = *jt;
-							if (arrivals.size() > 1)
-								jt++;
+						if (it->second.flags == 0)
+							arrivals.emplace_back(it->second.as_int());
+						else {
+							for (const auto &tok : split_tokens(it->second.decode_string()))
+								arrivals.push_back(atoi(tok.c_str()));
+							if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
+								log_error("%s.%s is %d bits wide but abc9_arrival = '%s' has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
+										GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
 						}
 					}
 
-					if (abc9_flop)
+					if (arrivals.empty())
 						continue;
+
+					auto jt = arrivals.begin();
+#ifndef NDEBUG
+					if (ys_debug(1)) {
+						static std::set<std::pair<IdString,IdString>> seen;
+						if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
+					}
+#endif
+					for (auto bit : sigmap(conn.second)) {
+						arrival_times[bit] = *jt;
+						if (arrivals.size() > 1)
+							jt++;
+					}
 				}
+
+				if (abc9_flop)
+					continue;
 			}
 
 			bool cell_known = inst_module || cell->known();
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fc82f0e5f..5e650230d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -192,7 +192,7 @@ struct Abc9Pass : public ScriptPass
 		cleanup = true;
 		lut_mode = false;
 		maxlut = 0;
-		box_file = "(null)";
+		box_file = "";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -286,9 +286,9 @@ struct Abc9Pass : public ScriptPass
 			else if (!lut_mode)
 				run(stringf("abc9_ops -prep_lut %d", maxlut));
 			if (help_mode)
-				run("abc9_ops -prep_box [<-box>|(null)]");
-			else
-				run(stringf("abc9_ops -prep_box %s", box_file.c_str()));
+				run("abc9_ops -prep_box [-dff]", "(skip if -box)");
+			else if (box_file.empty())
+				run(stringf("abc9_ops -prep_box %s", dff_mode ? "-dff" : ""));
 			run("select -set abc9_holes A:abc9_holes");
 			run("flatten -wb @abc9_holes");
 			run("techmap @abc9_holes");
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index e1ab70f11..f3d3381cd 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -378,7 +378,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	}
 }
 
-void prep_delays(RTLIL::Design *design)
+void prep_delays(RTLIL::Design *design, bool dff_mode)
 {
 	// Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
 	//   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
@@ -407,7 +407,7 @@ void prep_delays(RTLIL::Design *design)
 			log_assert(inst_module);
 			blackboxes.insert(inst_module);
 
-			if (inst_module->get_bool_attribute(ID(abc9_flop))) {
+			if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
 				flops.insert(inst_module);
 				continue; // do not add $__ABC9_DELAY boxes to flops
 					  //   as delays will be captured in the flop box
@@ -474,10 +474,8 @@ void prep_delays(RTLIL::Design *design)
 			continue;
 
 		ports.clear();
-		for (const auto &i : arrivals) {
-			log_dump(i.first, i.first.wire->name);
+		for (const auto &i : arrivals)
 			ports.insert(i.first.wire);
-		}
 		for (auto wire : ports) {
 			log_assert(wire->port_output);
 			ss.str("");
@@ -537,7 +535,7 @@ void prep_delays(RTLIL::Design *design)
 		inst_module = design->module(derived_type);
 		log_assert(inst_module);
 
-		auto &cell_requireds = requireds_cache[cell->type];
+		auto &cell_requireds = requireds_cache[derived_type];
 		for (auto &conn : cell->connections_) {
 			auto port_wire = inst_module->wire(conn.first);
 			if (!port_wire->port_input)
@@ -569,7 +567,7 @@ void prep_delays(RTLIL::Design *design)
 #ifndef NDEBUG
 				if (ys_debug(1)) {
 					static std::set<std::pair<IdString,IdString>> seen;
-					if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
+					if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
 				}
 #endif
 				auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
@@ -652,64 +650,66 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 	ofs.close();
 }
 
-void prep_box(RTLIL::Design *design)
+void prep_box(RTLIL::Design *design, bool dff_mode)
 {
 	std::stringstream ss;
 	int abc9_box_id = 1;
 	dict<IdString,std::vector<IdString>> box_ports;
 	for (auto module : design->modules()) {
-		if (module->get_bool_attribute(ID(abc9_flop))) {
-			int num_inputs = 0, num_outputs = 0;
-			for (auto port_name : module->ports) {
-				auto wire = module->wire(port_name);
-				log_assert(GetSize(wire) == 1);
-				if (wire->port_input) num_inputs++;
-				if (wire->port_output) num_outputs++;
+		auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
+		if (abc9_flop) {
+			if (dff_mode) {
+				int num_inputs = 0, num_outputs = 0;
+				for (auto port_name : module->ports) {
+					auto wire = module->wire(port_name);
+					log_assert(GetSize(wire) == 1);
+					if (wire->port_input) num_inputs++;
+					if (wire->port_output) num_outputs++;
+				}
+				log_assert(num_outputs == 1);
+
+				auto r = module->attributes.insert(ID(abc9_box_id));
+				if (r.second)
+					r.first->second = abc9_box_id++;
+
+				ss << log_id(module) << " " << r.first->second.as_int();
+				ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+				ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+
+				ss << "#";
+				bool first = true;
+				for (auto port_name : module->ports) {
+					auto wire = module->wire(port_name);
+					if (!wire->port_input)
+						continue;
+					if (first)
+						first = false;
+					else
+						ss << " ";
+					ss << log_id(wire);
+				}
+				ss << " abc9_ff.Q" << std::endl;
+
+				first = true;
+				for (auto port_name : module->ports) {
+					auto wire = module->wire(port_name);
+					if (!wire->port_input)
+						continue;
+					if (first)
+						first = false;
+					else
+						ss << " ";
+					ss << wire->attributes.at("\\abc9_required", 0).as_int();
+				}
+				// Last input is 'abc9_ff.Q'
+				ss << " 0" << std::endl << std::endl;
+				continue;
 			}
-			log_assert(num_outputs == 1);
-
-			auto r = module->attributes.insert(ID(abc9_box_id));
-			if (r.second)
-				r.first->second = abc9_box_id++;
-
-			ss << log_id(module) << " " << r.first->second.as_int();
-			ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
-			ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
-
-			ss << "#";
-			bool first = true;
-			for (auto port_name : module->ports) {
-				auto wire = module->wire(port_name);
-				if (!wire->port_input)
-					continue;
-				if (first)
-					first = false;
-				else
-					ss << " ";
-				ss << log_id(wire);
-			}
-			ss << " abc9_ff.Q" << std::endl;
-
-			first = true;
-			for (auto port_name : module->ports) {
-				auto wire = module->wire(port_name);
-				if (!wire->port_input)
-					continue;
-				if (first)
-					first = false;
-				else
-					ss << " ";
-				ss << wire->attributes.at("\\abc9_required", 0).as_int();
-			}
-			// Last input is 'abc9_ff.Q'
-			ss << " 0" << std::endl << std::endl;
-			continue;
 		}
-
-		auto it = module->attributes.find(ID(abc9_box));
-		if (it == module->attributes.end())
-			continue;
-		module->attributes.erase(it);
+		else {
+			if (!module->attributes.erase(ID(abc9_box)))
+				continue;
+		}
 		log_assert(!module->attributes.count(ID(abc9_box_id)));
 
 		dict<std::pair<SigBit,SigBit>, std::string> table;
@@ -1241,8 +1241,8 @@ struct Abc9OpsPass : public Pass {
 		log("        whiteboxes.\n");
 		log("\n");
 		log("    -dff\n");
-		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
-		log("        during -prep_xaiger.\n");
+		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
+		log("        during -prep_{delays,xaiger,box}.\n");
 		log("\n");
 		log("    -prep_dff\n");
 		log("        compute the clock domain and initial value of each flop in the design.\n");
@@ -1345,17 +1345,17 @@ struct Abc9OpsPass : public Pass {
 		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
 			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
 
-		if (dff_mode && !prep_xaiger_mode)
-			log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
+		if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode)
+			log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n");
 
 		if (check_mode)
 			check(design);
 		if (prep_delays_mode)
-			prep_delays(design);
+			prep_delays(design, dff_mode);
 		if (prep_lut_mode)
 			prep_lut(design, maxlut);
 		if (prep_box_mode)
-			prep_box(design);
+			prep_box(design, dff_mode);
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 0be53ef9e..4b094fb5b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -492,8 +492,8 @@ module FDRE (
   endgenerate
   specify
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249
-    //$setup(D , posedge C &&& CE &&& !IS_C_INVERTED , -46); // Negative times not currently supported
-    //$setup(D , negedge C &&& CE &&&  IS_C_INVERTED , -46); // Negative times not currently supported
+    //$setup(D , posedge C &&& CE && !IS_C_INVERTED , -46); // Negative times not currently supported
+    //$setup(D , negedge C &&& CE &&  IS_C_INVERTED , -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE, posedge C &&& !IS_C_INVERTED, 109);
     $setup(CE, negedge C &&&  IS_C_INVERTED, 109);
@@ -665,6 +665,7 @@ module FDCE (
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
     $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(CLR, posedge C &&& !IS_C_INVERTED, 404);
     $setup(CLR, negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
@@ -692,6 +693,7 @@ module FDCE_1 (
     //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , negedge C, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(CLR, negedge C, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
     //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0
@@ -730,6 +732,7 @@ module FDPE (
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , posedge C &&& !IS_C_INVERTED, 109);
     $setup(CE , negedge C &&&  IS_C_INVERTED, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(PRE, posedge C &&& !IS_C_INVERTED, 404);
     $setup(PRE, negedge C &&&  IS_C_INVERTED, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
@@ -757,6 +760,7 @@ module FDPE_1 (
     //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248
     $setup(CE , negedge C, 109);
+    // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274
     $setup(PRE, negedge C, 404);
     // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
     //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1

From 977262c8033b8778a32d4f29a77c64ea5a2799bd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 12:13:12 -0800
Subject: [PATCH 19/46] Update simple_abc9 tests

---
 tests/simple_abc9/abc.box     | 2 --
 tests/simple_abc9/abc9.v      | 7 ++++++-
 tests/simple_abc9/run-test.sh | 4 ++--
 3 files changed, 8 insertions(+), 5 deletions(-)
 delete mode 100644 tests/simple_abc9/abc.box

diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box
deleted file mode 100644
index a8801d807..000000000
--- a/tests/simple_abc9/abc.box
+++ /dev/null
@@ -1,2 +0,0 @@
-MUXF8 1 0 3 1
-1 1 1
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index e5837d480..688b47586 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -213,8 +213,13 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode
   input rst;
 endmodule
 
-(* abc9_box_id=1, whitebox *)
+(* abc9_box, blackbox *)
 module MUXF8(input I0, I1, S, output O);
+specify
+    (I0 => O) = 0;
+    (I1 => O) = 0;
+    (S => O) = 0;
+endspecify
 endmodule
 
 // Citation: https://github.com/alexforencich/verilog-ethernet
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 32d7a80ca..424d8f417 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -25,8 +25,8 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p
     synth -run coarse; \
     opt -full; \
     techmap; \
-    abc9 -lut 4 -box ../abc.box; \
+    abc9 -lut 4; \
     clean; \
     check -assert; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \
-    setattr -mod -unset whitebox'"
+    setattr -mod -unset blackbox'"

From aac309626b4829b8d6efec1854bccf84c0bd0b20 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 13:43:33 -0800
Subject: [PATCH 20/46] Fix tests by gating some specify constructs from
 iverilog

---
 techlibs/xilinx/cells_sim.v | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 4b094fb5b..5dadf1ef3 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -269,6 +269,7 @@ endmodule
 //   cost of 3-input LUTs and is not intended to be instantiated
 (* abc9_lut=10 *)
 module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
+`ifndef __ICARUS__
   specify
                                                  // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
     (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
@@ -279,12 +280,14 @@ module \$__ABC9_LUT7 (output O, input I0, I1, I2, I3, I4, I5, I6);
     (I5 => O) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
     (I6 => O) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
   endspecify
+`endif
 endmodule
 
 // This is a placeholder for ABC9 to extract the area/delay
 //   cost of 3-input LUTs and is not intended to be instantiated
 (* abc9_lut=20 *)
 module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
+`ifndef __ICARUS__
   specify
                                                                              // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L716
     (I0 => O) = 642 + 223 /* to cross F7BMUX */ + 104 /* to cross F8MUX */ + 192 /* BMUX */;
@@ -296,6 +299,7 @@ module \$__ABC9_LUT8 (output O, input I0, I1, I2, I3, I4, I5, I6, I7);
     (I6 => O) = 0 + 296 /* to select F7BMUX */  + 104 /* to cross F8MUX */ + 192 /* BMUX */;
     (I7 => O) = 0 + 0 + 273 /* to select F8MUX */ + 192 /* BMUX */;
   endspecify
+`endif
 endmodule
 
 module MUXCY(output O, input CI, DI, S);
@@ -1417,9 +1421,11 @@ module RAM32X1D (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
     $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
     $setup(A4, posedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+`endif
     // Captured by $__ABC9_RAM6
     //({A0,DPRA0} => {SPO,DPO}) = 642;
     //({A1,DPRA1} => {SPO,DPO}) = 631;
@@ -1467,8 +1473,10 @@ module RAM32X1D_1 (
     $setup(A3, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
     $setup(A4, negedge WCLK &&& WE, 66);
+`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+`endif
     // Captured by $__ABC9_RAM6
     //({A0,DPRA0} => {SPO,DPO}) = 642;
     //({A1,DPRA1} => {SPO,DPO}) = 631;
@@ -1522,9 +1530,11 @@ module RAM64X1D (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
     $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
     $setup(A5, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+`endif
     // Captured by $__ABC9_RAM6
     //({A0,DPRA0} => {SPO,DPO}) = 642;
     //({A1,DPRA1} => {SPO,DPO}) = 631;
@@ -1571,8 +1581,10 @@ module RAM64X1D_1 (
     $setup(A4, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
     $setup(A5, negedge WCLK &&& WE, 66);
+`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
+`endif
   endspecify
 endmodule
 
@@ -1615,9 +1627,11 @@ module RAM128X1D (
     $setup(A[5], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 68);
     $setup(A[6], posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
     $setup(A[6], negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
+`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
     if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153 + 217 /* to cross F7AMUX */ + 175 /* AMUX */;
     if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+`endif
     // Captured by $__ABC9_RAM7
     //(A[0] => SPO) = 642 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
     //(A[1] => SPO) = 631 + 193 /* to cross F7AMUX */ + 175 /* AMUX */;
@@ -2380,6 +2394,7 @@ parameter RSTTYPE = "SYNC";
 
 // This is a strict subset of Spartan 6 -- reuse its model.
 
+/* verilator lint_off PINMISSING */
 DSP48A1 #(
 	.A0REG(A0REG),
 	.A1REG(A1REG),
@@ -2426,6 +2441,7 @@ DSP48A1 #(
 	.RSTOPMODE(RSTOPMODE),
 	.RSTP(RSTP)
 );
+/* verilator lint_on PINMISSING */
 
 endmodule
 

From 3728ef1765b3b3375481222832d3a17600ae0312 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 09:17:20 -0800
Subject: [PATCH 21/46] ice40: fix specify for inverted clocks

---
 techlibs/ice40/cells_sim.v | 54 +++++++++++++++++++-------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 380935569..0b7fdd2a9 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1507,11 +1507,11 @@ module SB_RAM40_4KNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
 		$setup(MASK, posedge WCLK &&& WE && WCLKE, 274);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
-		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 203);
+		$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
-		$setup(RCLKE, negedge RCLK, 267);
+		$setup(RCLKE, posedge RCLKN, 267);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
-		$setup(RE, negedge RCLK, 98);
+		$setup(RE, posedge RCLKN, 98);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
 		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 224);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
@@ -1521,7 +1521,7 @@ module SB_RAM40_4KNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
 		$setup(WE, posedge WCLK, 133);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-		(negedge RCLK => (RDATA : 16'bx)) = 2146;
+		(posedge RCLKN => (RDATA : 16'bx)) = 2146;
 	endspecify
 `endif
 `ifdef ICE40_LP
@@ -1529,11 +1529,11 @@ module SB_RAM40_4KNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
 		$setup(MASK, posedge WCLK &&& WE && WCLKE, 403);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
-		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 300);
+		$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
-		$setup(RCLKE, negedge RCLK, 393);
+		$setup(RCLKE, posedge RCLKN, 393);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
-		$setup(RE, negedge RCLK, 145);
+		$setup(RE, posedge RCLKN, 145);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
 		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 331);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
@@ -1543,7 +1543,7 @@ module SB_RAM40_4KNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
 		$setup(WE, posedge WCLK, 196);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-		(negedge RCLK => (RDATA : 16'bx)) = 3163;
+		(posedge RCLKN => (RDATA : 16'bx)) = 3163;
 	endspecify
 `endif
 `ifdef ICE40_U
@@ -1551,11 +1551,11 @@ module SB_RAM40_4KNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
 		$setup(MASK, posedge WCLK &&& WE && WCLKE, 517);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
-		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 384);
+		$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
-		$setup(RCLKE, negedge RCLK, 503);
+		$setup(RCLKE, posedge RCLKN, 503);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
-		$setup(RE, negedge RCLK, 185);
+		$setup(RE, posedge RCLKN, 185);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
 		$setup(WADDR, posedge WCLK &&& WE && WCLKE, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
@@ -1565,7 +1565,7 @@ module SB_RAM40_4KNR (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
 		$setup(WE, posedge WCLK, 252);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
-		(negedge RCLK => (RDATA : 16'bx)) = 1179;
+		(posedge RCLKN => (RDATA : 16'bx)) = 1179;
 	endspecify
 `endif
 endmodule
@@ -1636,7 +1636,7 @@ module SB_RAM40_4KNW (
 `ifdef ICE40_HX
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
-		$setup(MASK, negedge WCLK &&& WE && WCLKE, 274);
+		$setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
 		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
@@ -1644,13 +1644,13 @@ module SB_RAM40_4KNW (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
 		$setup(RE, posedge RCLK, 98);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
-		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 224);
+		$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
-		$setup(WCLKE, negedge WCLK, 267);
+		$setup(WCLKE, posedge WCLKN, 267);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
-		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 161);
+		$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
-		$setup(WE, negedge WCLK, 133);
+		$setup(WE, posedge WCLKN, 133);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
 		(posedge RCLK => (RDATA : 16'bx)) = 2146;
 	endspecify
@@ -1658,7 +1658,7 @@ module SB_RAM40_4KNW (
 `ifdef ICE40_LP
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
-		$setup(MASK, negedge WCLK &&& WE && WCLKE, 403);
+		$setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
 		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 300);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
@@ -1666,13 +1666,13 @@ module SB_RAM40_4KNW (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
 		$setup(RE, posedge RCLK, 145);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
-		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 331);
+		$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
-		$setup(WCLKE, negedge WCLK, 393);
+		$setup(WCLKE, posedge WCLKN, 393);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
-		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 238);
+		$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
-		$setup(WE, negedge WCLK, 196);
+		$setup(WE, posedge WCLKN, 196);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
 		(posedge RCLK => (RDATA : 16'bx)) = 3163;
 	endspecify
@@ -1680,7 +1680,7 @@ module SB_RAM40_4KNW (
 `ifdef ICE40_U
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
-		$setup(MASK, negedge WCLK &&& WE && WCLKE, 517);
+		$setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
 		$setup(RADDR, posedge RCLK &&& RE && RCLKE, 384);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
@@ -1688,13 +1688,13 @@ module SB_RAM40_4KNW (
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
 		$setup(RE, posedge RCLK, 185);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
-		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 424);
+		$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
-		$setup(WCLKE, negedge WCLK, 503);
+		$setup(WCLKE, posedge WCLKN, 503);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
-		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 305);
+		$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
-		$setup(WE, negedge WCLK, 252);
+		$setup(WE, posedge WCLKN, 252);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
 		(posedge RCLK => (RDATA : 16'bx)) = 1179;
 	endspecify

From 7d86aceee326d214b9e31602f00f6196d1213c9e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 09:17:53 -0800
Subject: [PATCH 22/46] Expand +/xilinx/cells_sim.v to keep ICARUS and non
 -specify paresr happy

---
 techlibs/xilinx/cells_sim.v | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5dadf1ef3..4873a66f3 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1421,11 +1421,11 @@ module RAM32X1D (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
     $setup(A4, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
     $setup(A4, posedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
-`endif
+    if (!IS_WCLK_INVERTED) (posedge WCLK => (SPO : D))    = 1153;
+    if (!IS_WCLK_INVERTED) (posedge WCLK => (DPO : 1'bx)) = 1153;
+    if ( IS_WCLK_INVERTED) (posedge WCLK => (SPO : D))    = 1153;
+    if ( IS_WCLK_INVERTED) (negedge WCLK => (DPO : 1'bx)) = 1153;
     // Captured by $__ABC9_RAM6
     //({A0,DPRA0} => {SPO,DPO}) = 642;
     //({A1,DPRA1} => {SPO,DPO}) = 631;
@@ -1473,10 +1473,9 @@ module RAM32X1D_1 (
     $setup(A3, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L792
     $setup(A4, negedge WCLK &&& WE, 66);
-`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
-`endif
+    if (WE) (negedge WCLK => (SPO : D))    = 1153;
+    if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
     // Captured by $__ABC9_RAM6
     //({A0,DPRA0} => {SPO,DPO}) = 642;
     //({A1,DPRA1} => {SPO,DPO}) = 631;
@@ -1530,11 +1529,11 @@ module RAM64X1D (
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
     $setup(A5, posedge WCLK &&& !IS_WCLK_INVERTED && WE, 66);
     $setup(A5, negedge WCLK &&&  IS_WCLK_INVERTED && WE, 66);
-`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
-    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
-`endif
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (SPO : D))    = 1153;
+    if (!IS_WCLK_INVERTED && WE) (posedge WCLK => (DPO : 1'bx)) = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (SPO : D))    = 1153;
+    if ( IS_WCLK_INVERTED && WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
     // Captured by $__ABC9_RAM6
     //({A0,DPRA0} => {SPO,DPO}) = 642;
     //({A1,DPRA1} => {SPO,DPO}) = 631;
@@ -1581,10 +1580,9 @@ module RAM64X1D_1 (
     $setup(A4, negedge WCLK &&& WE, 68);
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L818
     $setup(A5, negedge WCLK &&& WE, 66);
-`ifndef __ICARUS__
     // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/31f51ac5ec7448dd6f79a8267f147123e4413c21/artix7/timings/CLBLM_R.sdf#L981
-    if (WE) (negedge WCLK => ({SPO,DPO} : {D,1'bx})) = 1153;
-`endif
+    if (WE) (negedge WCLK => (SPO : D))    = 1153;
+    if (WE) (negedge WCLK => (DPO : 1'bx)) = 1153;
   endspecify
 endmodule
 

From bc97e64b211ea4ff99afde7cd1f130b1b3261848 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 10:31:38 -0800
Subject: [PATCH 23/46] Fix tests/arch/xilinx/fsm.ys to count flops only

---
 tests/arch/xilinx/fsm.ys | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index fec4c6082..70c05f2c0 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -15,10 +15,7 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 4 t:FDRE
 select -assert-count 1 t:FDSE
-select -assert-count 1 t:LUT2
-select -assert-count 3 t:LUT5
-select -assert-count 1 t:LUT6
-select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:FDSE t:LUT* %% t:* %D
 
 design -load orig
 
@@ -31,8 +28,5 @@ cd fsm # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 6 t:FDRE
-select -assert-count 1 t:LUT1
-select -assert-count 3 t:LUT3
-select -assert-count 6 t:LUT4
-select -assert-count 6 t:MUXF5
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D
+# FIXME: One more register than above?
+select -assert-none t:BUFG t:FDRE t:LUT* t:MUXF* %% t:* %D

From cda4acb544614711b2c187e93f515bfc43ca8da1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 11:11:34 -0800
Subject: [PATCH 24/46] abc9_ops: add and use new TimingInfo struct

---
 kernel/timinginfo.h        | 173 +++++++++++++++++++++++++++++++++++++
 passes/techmap/abc9_ops.cc | 111 +++++++++---------------
 2 files changed, 214 insertions(+), 70 deletions(-)
 create mode 100644 kernel/timinginfo.h

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
new file mode 100644
index 000000000..8c16fff6c
--- /dev/null
+++ b/kernel/timinginfo.h
@@ -0,0 +1,173 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *            (C) 2020  Eddie Hung    <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef TIMINGARCS_H
+#define TIMINGARCS_H
+
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+typedef std::pair<RTLIL::SigBit,RTLIL::SigBit> BitBit;
+
+struct ModuleTiming
+{
+	RTLIL::IdString type;
+	dict<BitBit, int> comb;
+	dict<RTLIL::SigBit, int> arrival, required;
+};
+
+struct TimingInfo
+{
+        dict<RTLIL::IdString, ModuleTiming> data;
+
+	TimingInfo()
+	{
+	}
+
+	TimingInfo(RTLIL::Design *design)
+	{
+		setup(design);
+	}
+
+	void setup(RTLIL::Design *design)
+	{
+		for (auto module : design->modules()) {
+			if (!module->get_blackbox_attribute())
+				continue;
+			setup_module(module);
+                }
+	}
+
+	void setup_module(RTLIL::Module *module)
+	{
+                auto r = data.insert(module->name);
+                log_assert(r.second);
+                auto &t = r.first->second;
+
+		for (auto cell : module->cells()) {
+                        if (cell->type == ID($specify2)) {
+                                auto src = cell->getPort(ID(SRC));
+                                auto dst = cell->getPort(ID(DST));
+                                for (const auto &c : src.chunks())
+                                        if (!c.wire->port_input)
+                                                log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+                                for (const auto &c : dst.chunks())
+                                        if (!c.wire->port_output)
+                                                log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
+                                int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
+                                int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+                                int max = std::max(rise_max,fall_max);
+                                if (max < 0)
+                                        log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
+                                if (cell->getParam(ID(FULL)).as_bool()) {
+                                        for (const auto &s : src)
+                                                for (const auto &d : dst) {
+                                                        auto r = t.comb.insert(BitBit(s,d));
+                                                        if (!r.second)
+                                                                log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
+                                                        r.first->second = max;
+                                                }
+                                }
+                                else {
+                                        log_assert(GetSize(src) == GetSize(dst));
+                                        for (auto i = 0; i < GetSize(src); i++) {
+                                                const auto &s = src[i];
+                                                const auto &d = dst[i];
+                                                auto r = t.comb.insert(BitBit(s,d));
+                                                if (!r.second)
+                                                        log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
+                                                r.first->second = max;
+                                        }
+                                }
+                        }
+                        else if (cell->type == ID($specify3)) {
+				auto src = cell->getPort(ID(SRC));
+				auto dst = cell->getPort(ID(DST));
+				for (const auto &c : src.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+				for (const auto &c : dst.chunks())
+					if (!c.wire->port_output)
+						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
+				int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
+				int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+				int max = std::max(rise_max,fall_max);
+				if (max < 0)
+					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+				if (max <= 0) {
+					log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+					continue;
+				}
+				for (const auto &d : dst) {
+                                        auto &v = t.arrival[d];
+					v = std::max(v, max);
+                                }
+			}
+			else if (cell->type == ID($specrule)) {
+				auto type = cell->getParam(ID(TYPE)).decode_string();
+				if (type != "$setup" && type != "$setuphold")
+					continue;
+				auto src = cell->getPort(ID(SRC));
+				auto dst = cell->getPort(ID(DST));
+				for (const auto &c : src.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+				for (const auto &c : dst.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
+				int max = cell->getParam(ID(T_LIMIT_MAX)).as_int();
+				if (max < 0)
+					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+				if (max <= 0) {
+					log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
+					continue;
+				}
+				for (const auto &s : src) {
+                                        auto &v = t.required[s];
+					v = std::max(v, max);
+                                }
+			}
+		}
+	}
+
+        int delay(IdString module_name, const SigBit &src, const SigBit &dst) const {
+                auto it = data.find(module_name);
+                if (it == data.end())
+                        return 0;
+                return it->second.comb.at(BitBit(src,dst), 0);
+        }
+        int arrival(IdString module_name, const SigBit &src) const {
+                auto it = data.find(module_name);
+                if (it == data.end())
+                        return 0;
+                return it->second.arrival.at(src, 0);
+        }
+        int required(IdString module_name, const SigBit &dst) const {
+                auto it = data.find(module_name);
+                if (it == data.end())
+                        return 0;
+                return it->second.required.at(dst, 0);
+        }
+};
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index f3d3381cd..0a5d88a34 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -22,6 +22,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/utils.h"
 #include "kernel/celltypes.h"
+#include "kernel/timinginfo.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -380,9 +381,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design, bool dff_mode)
 {
-	// Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
+	// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
 	//   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
-	pool<Module*> blackboxes;
 	pool<Module*> flops;
 	std::vector<Cell*> cells;
 	for (auto module : design->selected_modules()) {
@@ -405,7 +405,6 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 			IdString blackboxes_type = inst_module->derive(design, cell->parameters);
 			inst_module = design->module(blackboxes_type);
 			log_assert(inst_module);
-			blackboxes.insert(inst_module);
 
 			if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
 				flops.insert(inst_module);
@@ -417,70 +416,33 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 		}
 	}
 
+        const TimingInfo timing(design);
+
 	// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
-	dict<SigBit, int> arrivals, requireds;
+        // TODO: Deprecate
 	pool<Wire*> ports;
 	std::stringstream ss;
-	for (auto module : blackboxes) {
-		arrivals.clear();
-		requireds.clear();
-		for (auto cell : module->cells()) {
-			if (cell->type == ID($specify3)) {
-				auto src = cell->getPort(ID(SRC));
-				auto dst = cell->getPort(ID(DST));
-				for (const auto &c : src.chunks())
-					if (!c.wire->port_input)
-						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-				for (const auto &c : dst.chunks())
-					if (!c.wire->port_output)
-						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-				int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
-				int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
-				int max = std::max(rise_max,fall_max);
-				if (max < 0)
-					log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-				if (max <= 0) {
-					log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-					continue;
-				}
-				for (const auto &d : dst)
-					arrivals[d] = std::max(arrivals[d], max);
-			}
-			else if (cell->type == ID($specrule)) {
-				auto type = cell->getParam(ID(TYPE)).decode_string();
-				if (type != "$setup" && type != "$setuphold")
-					continue;
-				auto src = cell->getPort(ID(SRC));
-				auto dst = cell->getPort(ID(DST));
-				for (const auto &c : src.chunks())
-					if (!c.wire->port_input)
-						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-				for (const auto &c : dst.chunks())
-					if (!c.wire->port_input)
-						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
-				int setup = cell->getParam(ID(T_LIMIT_MAX)).as_int();
-				if (setup < 0)
-					log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-				if (setup <= 0) {
-					log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
-					continue;
-				}
-				for (const auto &s : src)
-					requireds[s] = std::max(requireds[s], setup);
-			}
-		}
+	for (auto module : design->modules()) {
 
-		if (arrivals.empty() && requireds.empty())
-			continue;
+                auto it = timing.data.find(module->name);
+                if (it == timing.data.end())
+                        continue;
+
+                const auto &t = it->second;
+                if (t.arrival.empty() && t.required.empty())
+                        continue;
+
+                const auto &arrival = t.arrival;
+                const auto &required = t.required;
 
 		ports.clear();
-		for (const auto &i : arrivals)
+		for (const auto &i : arrival)
 			ports.insert(i.first.wire);
 		for (auto wire : ports) {
 			log_assert(wire->port_output);
 			ss.str("");
 			if (GetSize(wire) == 1)
-				wire->attributes[ID(abc9_arrival)] = arrivals.at(SigBit(wire,0));
+				wire->attributes[ID(abc9_arrival)] = arrival.at(SigBit(wire,0));
 			else {
 				bool first = true;
 				for (auto b : SigSpec(wire)) {
@@ -488,24 +450,20 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 						first = false;
 					else
 						ss << " ";
-					auto it = arrivals.find(b);
-					if (it == arrivals.end())
-						ss << "0";
-					else
-						ss << it->second;
+                                        ss << arrival.at(b, 0);
 				}
 				wire->attributes[ID(abc9_arrival)] = ss.str();
 			}
 		}
 
 		ports.clear();
-		for (const auto &i : requireds)
+		for (const auto &i : required)
 			ports.insert(i.first.wire);
 		for (auto wire : ports) {
 			log_assert(wire->port_input);
 			ss.str("");
 			if (GetSize(wire) == 1)
-				wire->attributes[ID(abc9_required)] = requireds.at(SigBit(wire,0));
+				wire->attributes[ID(abc9_required)] = required.at(SigBit(wire,0));
 			else {
 				bool first = true;
 				for (auto b : SigSpec(wire)) {
@@ -513,11 +471,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 						first = false;
 					else
 						ss << " ";
-					auto it = requireds.find(b);
-					if (it == requireds.end())
-						ss << "0";
-					else
-						ss << it->second;
+                                        ss << required.at(b, 0);
 				}
 				wire->attributes[ID(abc9_required)] = ss.str();
 			}
@@ -567,7 +521,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 #ifndef NDEBUG
 				if (ys_debug(1)) {
 					static std::set<std::pair<IdString,IdString>> seen;
-					if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
+					if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = '%s'\n", log_id(cell->type), log_id(conn.first),
+                                                        port_wire->attributes.at("\\abc9_required").decode_string().c_str());
 				}
 #endif
 				auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
@@ -659,6 +614,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
 		if (abc9_flop) {
 			if (dff_mode) {
+                                log_dump(module->name);
 				int num_inputs = 0, num_outputs = 0;
 				for (auto port_name : module->ports) {
 					auto wire = module->wire(port_name);
@@ -699,7 +655,22 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 						first = false;
 					else
 						ss << " ";
-					ss << wire->attributes.at("\\abc9_required", 0).as_int();
+                                        auto it = wire->attributes.find("\\abc9_required");
+                                        if (it == wire->attributes.end())
+                                                ss << 0;
+                                        else {
+                                                log_assert(it->second.flags == 0);
+                                                ss << it->second.as_int();
+
+#ifndef NDEBUG
+                                                if (ys_debug(1)) {
+                                                        static std::set<std::pair<IdString,IdString>> seen;
+                                                        if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
+                                                                        log_id(port_name), it->second.as_int());
+                                                }
+#endif
+                                        }
+
 				}
 				// Last input is 'abc9_ff.Q'
 				ss << " 0" << std::endl << std::endl;

From 3ea5506f812879c0ecf66431efde002493e11bdf Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 11:41:43 -0800
Subject: [PATCH 25/46] abc9_ops: use TimingInfo for -prep_{lut,box} too

---
 kernel/timinginfo.h          |  20 +-----
 passes/techmap/abc9_ops.cc   | 125 +++++++++++++++--------------------
 techlibs/xilinx/abc9_model.v |  17 +++--
 3 files changed, 65 insertions(+), 97 deletions(-)

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 8c16fff6c..f31fbaab4 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -148,24 +148,8 @@ struct TimingInfo
 		}
 	}
 
-        int delay(IdString module_name, const SigBit &src, const SigBit &dst) const {
-                auto it = data.find(module_name);
-                if (it == data.end())
-                        return 0;
-                return it->second.comb.at(BitBit(src,dst), 0);
-        }
-        int arrival(IdString module_name, const SigBit &src) const {
-                auto it = data.find(module_name);
-                if (it == data.end())
-                        return 0;
-                return it->second.arrival.at(src, 0);
-        }
-        int required(IdString module_name, const SigBit &dst) const {
-                auto it = data.find(module_name);
-                if (it == data.end())
-                        return 0;
-                return it->second.required.at(dst, 0);
-        }
+        decltype(data)::const_iterator find (RTLIL::IdString module_name) const { return data.find(module_name); }
+        decltype(data)::const_iterator end () const { return data.end(); }
 };
 
 YOSYS_NAMESPACE_END
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 0a5d88a34..f55aeab85 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -424,8 +424,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 	std::stringstream ss;
 	for (auto module : design->modules()) {
 
-                auto it = timing.data.find(module->name);
-                if (it == timing.data.end())
+                auto it = timing.find(module->name);
+                if (it == timing.end())
                         continue;
 
                 const auto &t = it->second;
@@ -539,35 +539,31 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 
 void prep_lut(RTLIL::Design *design, int maxlut)
 {
+        const TimingInfo timing(design);
+
 	std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
 	for (auto module : design->modules()) {
 		auto it = module->attributes.find(ID(abc9_lut));
 		if (it == module->attributes.end())
 			continue;
+
+                auto jt = timing.find(module->name);
+                if (jt == timing.end())
+                        continue;
+
 		SigBit o;
 		std::vector<int> specify;
-		for (auto cell : module->cells()) {
-			if (cell->type != ID($specify2))
-				continue;
-			log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
-			log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
-			SigBit s = cell->getPort(ID(SRC));
-			SigBit d = cell->getPort(ID(DST));
-			log_assert(s.wire->port_input);
-			log_assert(d.wire->port_output);
+		auto &t = jt->second;
+		for (const auto &i : t.comb) {
+			auto &d = i.first.second;
+			log_dump(o, d);
 			if (o == SigBit())
 				o = d;
-			else
-				log_assert(o == d);
-			// TODO: Don't assume that each specify entry with the destination 'o'
-			//       describes a unique LUT input
-			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
-			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
-			int max = std::max(rise_max,fall_max);
-			if (max < 0)
-				log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
-			specify.push_back(max);
-		}
+			else if (o != d)
+				log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
+			specify.push_back(i.second);
+                }
+
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
 		// ABC requires non-decreasing LUT input delays
@@ -607,14 +603,27 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 
 void prep_box(RTLIL::Design *design, bool dff_mode)
 {
+        const TimingInfo timing(design);
+
 	std::stringstream ss;
 	int abc9_box_id = 1;
+	for (auto module : design->modules()) {
+		auto it = module->attributes.find(ID(abc9_box_id));
+		if (it == module->attributes.end())
+			continue;
+		abc9_box_id = std::max(abc9_box_id, it->second.as_int());
+	}
+
 	dict<IdString,std::vector<IdString>> box_ports;
 	for (auto module : design->modules()) {
 		auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
 		if (abc9_flop) {
+			auto r = module->attributes.insert(ID(abc9_box_id));
+			if (!r.second)
+				continue;
+			r.first->second = abc9_box_id++;
+
 			if (dff_mode) {
-                                log_dump(module->name);
 				int num_inputs = 0, num_outputs = 0;
 				for (auto port_name : module->ports) {
 					auto wire = module->wire(port_name);
@@ -624,10 +633,6 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 				}
 				log_assert(num_outputs == 1);
 
-				auto r = module->attributes.insert(ID(abc9_box_id));
-				if (r.second)
-					r.first->second = abc9_box_id++;
-
 				ss << log_id(module) << " " << r.first->second.as_int();
 				ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
 				ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
@@ -680,12 +685,12 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		else {
 			if (!module->attributes.erase(ID(abc9_box)))
 				continue;
-		}
-		log_assert(!module->attributes.count(ID(abc9_box_id)));
 
-		dict<std::pair<SigBit,SigBit>, std::string> table;
-		std::vector<SigBit> inputs;
-		std::vector<SigBit> outputs;
+			auto r = module->attributes.insert(ID(abc9_box_id));
+			if (!r.second)
+				continue;
+			r.first->second = abc9_box_id++;
+		}
 
 		auto r = box_ports.insert(module->name);
 		if (r.second) {
@@ -712,6 +717,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 			}
 		}
 
+		std::vector<SigBit> inputs;
+		std::vector<SigBit> outputs;
 		for (auto port_name : r.first->second) {
 			auto wire = module->wire(port_name);
 			if (wire->port_input)
@@ -721,47 +728,11 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 				for (int i = 0; i < GetSize(wire); i++)
 					outputs.emplace_back(wire, i);
 		}
-		for (auto cell : module->cells()) {
-			if (cell->type != ID($specify2))
-				continue;
-			auto src = cell->getPort(ID(SRC));
-			auto dst = cell->getPort(ID(DST));
-			for (const auto &c : src.chunks())
-				if (!c.wire->port_input)
-					log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-			for (const auto &c : dst.chunks())
-				if (!c.wire->port_output)
-					log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-			int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
-			int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
-			int max = std::max(rise_max,fall_max);
-			if (max < 0)
-				log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
-			if (cell->getParam(ID(FULL)).as_bool()) {
-				for (auto s : src)
-					for (auto d : dst) {
-						auto r = table.insert(std::make_pair(s,d));
-						log_assert(r.second);
-						r.first->second = std::to_string(max);
-					}
-			}
-			else {
-				log_assert(GetSize(src) == GetSize(dst));
-				for (auto i = 0; i < GetSize(src); i++) {
-					auto r = table.insert(std::make_pair(src[i],dst[i]));
-					if (!r.second)
-						log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(src[i]), log_signal(dst[i]));
-					log_assert(r.second);
-					r.first->second = std::to_string(max);
-				}
-			}
-		}
-		auto r2 = module->attributes.insert(ID(abc9_box_id));
-		log_assert(r2.second);
-		ss << log_id(module) << " " << abc9_box_id;
-		r2.first->second = abc9_box_id++;
+
+		ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int();
 		ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
 		ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
+
 		bool first = true;
 		ss << "#";
 		for (const auto &i : inputs) {
@@ -775,6 +746,12 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 				ss << log_id(i.wire) << "[" << i.offset << "]";
 		}
 		ss << std::endl;
+
+		auto it = timing.find(module->name);
+		if (it == timing.end())
+			log_error("(* abc9_box *) module '%s' has no timing information.\n", log_id(module));
+
+		const auto &t = it->second.comb;
 		for (const auto &o : outputs) {
 			first = true;
 			for (const auto &i : inputs) {
@@ -782,7 +759,11 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 					first = false;
 				else
 					ss << " ";
-				ss << table.at(std::make_pair(i,o), "-");
+				auto jt = t.find(std::make_pair(i,o));
+				if (jt == t.end())
+					ss << "-";
+				else
+					ss << jt->second;
 			}
 			ss << " # ";
 			if (GetSize(o.wire) == 1)
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v
index 8e2a05ceb..f83e97a2a 100644
--- a/techlibs/xilinx/abc9_model.v
+++ b/techlibs/xilinx/abc9_model.v
@@ -69,6 +69,7 @@ endmodule
 (* abc9_box *)
 module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
   specify
+    (A    => Y) =   0;
     (S[0] => Y) = 642;
     (S[1] => Y) = 631;
     (S[2] => Y) = 472;
@@ -81,13 +82,15 @@ endmodule
 (* abc9_box *)
 module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
   specify
-    (S[0] => Y) = 1028;
-    (S[1] => Y) = 1017;
-    (S[2] => Y) =  858;
-    (S[3] => Y) =  793;
-    (S[4] => Y) =  624;
-    (S[5] => Y) =  513;
-    (S[6] => Y) =  464;
+    (A    => Y) = 0;
+                                                    // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867
+    (S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */;
+    (S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */;
   endspecify
 endmodule
 

From a6fec9fe6052d2ec74fec4417be2fec45dea0df0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 12:01:03 -0800
Subject: [PATCH 26/46] abc9_ops: use TimingInfo for -prep_{lut,box} too

---
 kernel/timinginfo.h        |  5 ++++-
 passes/techmap/abc9_ops.cc | 42 ++++++++++++++++----------------------
 2 files changed, 22 insertions(+), 25 deletions(-)

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index f31fbaab4..b1a1b85ac 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -56,7 +56,7 @@ struct TimingInfo
                 }
 	}
 
-	void setup_module(RTLIL::Module *module)
+	const ModuleTiming& setup_module(RTLIL::Module *module)
 	{
                 auto r = data.insert(module->name);
                 log_assert(r.second);
@@ -146,10 +146,13 @@ struct TimingInfo
                                 }
 			}
 		}
+
+                return t;
 	}
 
         decltype(data)::const_iterator find (RTLIL::IdString module_name) const { return data.find(module_name); }
         decltype(data)::const_iterator end () const { return data.end(); }
+        int count (RTLIL::IdString module_name) const { return data.count(module_name); }
 };
 
 YOSYS_NAMESPACE_END
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index f55aeab85..80b19b471 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -381,6 +381,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design, bool dff_mode)
 {
+        TimingInfo timing;
+
 	// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
 	//   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
 	pool<Module*> flops;
@@ -412,23 +414,19 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 					  //   as delays will be captured in the flop box
 			}
 
+			if (!timing.count(inst_module->name))
+				timing.setup_module(inst_module);
+
 			cells.emplace_back(cell);
 		}
 	}
 
-        const TimingInfo timing(design);
-
 	// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
         // TODO: Deprecate
 	pool<Wire*> ports;
 	std::stringstream ss;
-	for (auto module : design->modules()) {
-
-                auto it = timing.find(module->name);
-                if (it == timing.end())
-                        continue;
-
-                const auto &t = it->second;
+	for (auto &i : timing.data) {
+                const auto &t = i.second;
                 if (t.arrival.empty() && t.required.empty())
                         continue;
 
@@ -539,7 +537,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 
 void prep_lut(RTLIL::Design *design, int maxlut)
 {
-        const TimingInfo timing(design);
+        TimingInfo timing;
 
 	std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
 	for (auto module : design->modules()) {
@@ -547,16 +545,12 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		if (it == module->attributes.end())
 			continue;
 
-                auto jt = timing.find(module->name);
-                if (jt == timing.end())
-                        continue;
+		auto &t = timing.setup_module(module);
 
 		SigBit o;
 		std::vector<int> specify;
-		auto &t = jt->second;
 		for (const auto &i : t.comb) {
 			auto &d = i.first.second;
-			log_dump(o, d);
 			if (o == SigBit())
 				o = d;
 			else if (o != d)
@@ -603,7 +597,7 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 
 void prep_box(RTLIL::Design *design, bool dff_mode)
 {
-        const TimingInfo timing(design);
+        TimingInfo timing;
 
 	std::stringstream ss;
 	int abc9_box_id = 1;
@@ -651,6 +645,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 				}
 				ss << " abc9_ff.Q" << std::endl;
 
+				auto &t = timing.setup_module(module).required;
 				first = true;
 				for (auto port_name : module->ports) {
 					auto wire = module->wire(port_name);
@@ -660,18 +655,18 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 						first = false;
 					else
 						ss << " ";
-                                        auto it = wire->attributes.find("\\abc9_required");
-                                        if (it == wire->attributes.end())
+                                        auto it = t.find(wire);
+                                        if (it == t.end())
+						// Assume that no setup time means zero
                                                 ss << 0;
                                         else {
-                                                log_assert(it->second.flags == 0);
-                                                ss << it->second.as_int();
+                                                ss << it->second;
 
 #ifndef NDEBUG
                                                 if (ys_debug(1)) {
                                                         static std::set<std::pair<IdString,IdString>> seen;
                                                         if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
-                                                                        log_id(port_name), it->second.as_int());
+                                                                        log_id(port_name), it->second);
                                                 }
 #endif
                                         }
@@ -747,11 +742,10 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		}
 		ss << std::endl;
 
-		auto it = timing.find(module->name);
-		if (it == timing.end())
+		auto &t = timing.setup_module(module).comb;
+		if (t.empty())
 			log_error("(* abc9_box *) module '%s' has no timing information.\n", log_id(module));
 
-		const auto &t = it->second.comb;
 		for (const auto &o : outputs) {
 			first = true;
 			for (const auto &i : inputs) {

From 1ef1ca812bd057fe0404893e357c10361225e393 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 12:54:47 -0800
Subject: [PATCH 27/46] Get rid of (* abc9_{arrival,required} *) entirely

---
 backends/aiger/xaiger.cc      |  44 +--
 kernel/timinginfo.h           |   7 +-
 passes/techmap/abc9_ops.cc    | 106 +------
 techlibs/xilinx/cells_sim.v   | 572 +++++++++++++++++++++++++++++-----
 techlibs/xilinx/cells_xtra.py |  76 +----
 techlibs/xilinx/cells_xtra.v  | 378 ----------------------
 6 files changed, 531 insertions(+), 652 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 16d48a932..2a39d225d 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -47,6 +47,7 @@ inline static uint32_t bswap32(uint32_t x)
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/utils.h"
+#include "kernel/timinginfo.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -184,7 +185,8 @@ struct XAigerWriter
 				}
 			}
 
-		dict<IdString,dict<IdString,std::vector<int>>> arrivals_cache;
+		TimingInfo timing;
+
 		for (auto cell : module->cells()) {
 			if (!cell->has_keep_attr()) {
 				if (cell->type == "$_NOT_")
@@ -252,43 +254,27 @@ struct XAigerWriter
 					}
 				}
 
-				auto &cell_arrivals = arrivals_cache[derived_type];
+				if (!timing.count(derived_type))
+					timing.setup_module(inst_module);
+				auto &t = timing.at(derived_type).arrival;
 				for (const auto &conn : cell->connections()) {
 					auto port_wire = inst_module->wire(conn.first);
 					if (!port_wire->port_output)
 						continue;
 
-					auto r = cell_arrivals.insert(conn.first);
-					auto &arrivals = r.first->second;
-					if (r.second) {
-						auto it = port_wire->attributes.find("\\abc9_arrival");
-						if (it == port_wire->attributes.end())
+					for (int i = 0; i < GetSize(conn.second); i++) {
+						auto d = t.at(SigBit(port_wire,i), 0);
+						if (d == 0)
 							continue;
-						if (it->second.flags == 0)
-							arrivals.emplace_back(it->second.as_int());
-						else {
-							for (const auto &tok : split_tokens(it->second.decode_string()))
-								arrivals.push_back(atoi(tok.c_str()));
-							if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire))
-								log_error("%s.%s is %d bits wide but abc9_arrival = '%s' has %d value(s)!\n", log_id(cell->type), log_id(conn.first),
-										GetSize(port_wire), log_signal(it->second), GetSize(arrivals));
-						}
-					}
 
-					if (arrivals.empty())
-						continue;
-
-					auto jt = arrivals.begin();
 #ifndef NDEBUG
-					if (ys_debug(1)) {
-						static std::set<std::pair<IdString,IdString>> seen;
-						if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt);
-					}
+						if (ys_debug(1)) {
+							static std::set<std::tuple<IdString,IdString,int>> seen;
+							if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_arrival = %d\n",
+									log_id(cell->type), log_id(conn.first), i, d);
+						}
 #endif
-					for (auto bit : sigmap(conn.second)) {
-						arrival_times[bit] = *jt;
-						if (arrivals.size() > 1)
-							jt++;
+						arrival_times[conn.second[i]] = d;
 					}
 				}
 
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index b1a1b85ac..9256c6445 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -150,9 +150,10 @@ struct TimingInfo
                 return t;
 	}
 
-        decltype(data)::const_iterator find (RTLIL::IdString module_name) const { return data.find(module_name); }
-        decltype(data)::const_iterator end () const { return data.end(); }
-        int count (RTLIL::IdString module_name) const { return data.count(module_name); }
+        decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
+        decltype(data)::const_iterator end() const { return data.end(); }
+        int count(RTLIL::IdString module_name) const { return data.count(module_name); }
+        const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
 };
 
 YOSYS_NAMESPACE_END
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 80b19b471..dad39828a 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -293,6 +293,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	holes_module->set_bool_attribute("\\abc9_holes");
 
 	dict<IdString, Cell*> cell_cache;
+	TimingInfo timing;
 
 	int port_id = 1, box_count = 0;
 	for (auto cell_name : toposort.sorted) {
@@ -404,8 +405,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 				continue;
 			if (inst_module->attributes.count(ID(abc9_box)))
 				continue;
-			IdString blackboxes_type = inst_module->derive(design, cell->parameters);
-			inst_module = design->module(blackboxes_type);
+			IdString derived_type = inst_module->derive(design, cell->parameters);
+			inst_module = design->module(derived_type);
 			log_assert(inst_module);
 
 			if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
@@ -414,71 +415,15 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 					  //   as delays will be captured in the flop box
 			}
 
-			if (!timing.count(inst_module->name))
+			if (!timing.count(derived_type))
 				timing.setup_module(inst_module);
 
 			cells.emplace_back(cell);
 		}
 	}
 
-	// Transform all $specify3 and $specrule to abc9_{arrival,required} attributes
-        // TODO: Deprecate
-	pool<Wire*> ports;
-	std::stringstream ss;
-	for (auto &i : timing.data) {
-                const auto &t = i.second;
-                if (t.arrival.empty() && t.required.empty())
-                        continue;
-
-                const auto &arrival = t.arrival;
-                const auto &required = t.required;
-
-		ports.clear();
-		for (const auto &i : arrival)
-			ports.insert(i.first.wire);
-		for (auto wire : ports) {
-			log_assert(wire->port_output);
-			ss.str("");
-			if (GetSize(wire) == 1)
-				wire->attributes[ID(abc9_arrival)] = arrival.at(SigBit(wire,0));
-			else {
-				bool first = true;
-				for (auto b : SigSpec(wire)) {
-					if (first)
-						first = false;
-					else
-						ss << " ";
-                                        ss << arrival.at(b, 0);
-				}
-				wire->attributes[ID(abc9_arrival)] = ss.str();
-			}
-		}
-
-		ports.clear();
-		for (const auto &i : required)
-			ports.insert(i.first.wire);
-		for (auto wire : ports) {
-			log_assert(wire->port_input);
-			ss.str("");
-			if (GetSize(wire) == 1)
-				wire->attributes[ID(abc9_required)] = required.at(SigBit(wire,0));
-			else {
-				bool first = true;
-				for (auto b : SigSpec(wire)) {
-					if (first)
-						first = false;
-					else
-						ss << " ";
-                                        ss << required.at(b, 0);
-				}
-				wire->attributes[ID(abc9_required)] = ss.str();
-			}
-		}
-	}
-
 	// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
-	//   with (* abc9_required *) attributes
-	dict<IdString,dict<IdString,std::vector<int>>> requireds_cache;
+	//   with required times
 	for (auto cell : cells) {
 		auto module = cell->module;
 		RTLIL::Module* inst_module = module->design->module(cell->type);
@@ -487,48 +432,29 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 		inst_module = design->module(derived_type);
 		log_assert(inst_module);
 
-		auto &cell_requireds = requireds_cache[derived_type];
+		auto &t = timing.at(derived_type).required;
 		for (auto &conn : cell->connections_) {
 			auto port_wire = inst_module->wire(conn.first);
 			if (!port_wire->port_input)
 				continue;
 
-			auto r = cell_requireds.insert(conn.first);
-			auto &requireds = r.first->second;
-			if (r.second) {
-				auto it = port_wire->attributes.find("\\abc9_required");
-				if (it == port_wire->attributes.end())
-					continue;
-				if (it->second.flags == 0) {
-					int delay = it->second.as_int();
-					requireds.emplace_back(delay);
-				}
-				else
-					for (const auto &tok : split_tokens(it->second.decode_string())) {
-						int delay = atoi(tok.c_str());
-						requireds.push_back(delay);
-					}
-			}
-
-			if (requireds.empty())
-				continue;
-
 			SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
-			auto it = requireds.begin();
-			for (int i = 0; i < GetSize(conn.second); ++i) {
+			for (int i = 0; i < GetSize(conn.second); i++) {
+				auto d = t.at(SigBit(port_wire,i), 0);
+				if (d == 0)
+					continue;
+
 #ifndef NDEBUG
 				if (ys_debug(1)) {
-					static std::set<std::pair<IdString,IdString>> seen;
-					if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = '%s'\n", log_id(cell->type), log_id(conn.first),
-                                                        port_wire->attributes.at("\\abc9_required").decode_string().c_str());
+					static std::set<std::tuple<IdString,IdString,int>> seen;
+					if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
+							log_id(cell->type), log_id(conn.first), i, d);
 				}
 #endif
 				auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
 				box->setPort(ID(I), conn.second[i]);
 				box->setPort(ID(O), O[i]);
-				box->setParam(ID(DELAY), *it);
-				if (requireds.size() > 1)
-					it++;
+				box->setParam(ID(DELAY), d);
 				conn.second[i] = O[i];
 			}
 		}
@@ -1172,7 +1098,7 @@ struct Abc9OpsPass : public Pass {
 		log("\n");
 		log("    -prep_delays\n");
 		log("        insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
-		log("        certain delays, e.g. (* abc9_required *) values.\n");
+		log("        certain required times.\n");
 		log("\n");
 		log("    -mark_scc\n");
 		log("        for an arbitrarily chosen cell in each unique SCC of each selected module\n");
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 4873a66f3..016324774 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -3058,133 +3058,133 @@ module DSP48E1 (
     parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
 
 `ifdef YOSYS
-    function integer \A.abc9_required ;
+    function integer \A.required ;
     begin
-        \A.abc9_required = 0;
-        if (AREG != 0)           \A.abc9_required =  254;
+        \A.required = 0;
+        if (AREG != 0)           \A.required =  254;
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-            if (MREG != 0)       \A.abc9_required = 1416;
-            else if (PREG != 0)  \A.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3030 : 2739) ;
+            if (MREG != 0)       \A.required = 1416;
+            else if (PREG != 0)  \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3030 : 2739) ;
         end
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
             // Worst-case from ADREG and MREG
-            if (MREG != 0)       \A.abc9_required = 2400;
-            else if (ADREG != 0) \A.abc9_required = 1283;
-            else if (PREG != 0)  \A.abc9_required = 3723;
-            else if (PREG != 0)  \A.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 4014 : 3723) ;
+            if (MREG != 0)       \A.required = 2400;
+            else if (ADREG != 0) \A.required = 1283;
+            else if (PREG != 0)  \A.required = 3723;
+            else if (PREG != 0)  \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 4014 : 3723) ;
         end
         else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)       \A.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1730 : 1441) ;
+            if (PREG != 0)       \A.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1730 : 1441) ;
         end
     end
     endfunction
-    function integer \B.abc9_required ;
+    function integer \B.required ;
     begin
-        \B.abc9_required = 0;
-        if (BREG != 0)      \B.abc9_required =  324;
-        else if (MREG != 0) \B.abc9_required = 1285;
+        \B.required = 0;
+        if (BREG != 0)      \B.required =  324;
+        else if (MREG != 0) \B.required = 1285;
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)  \B.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
+            if (PREG != 0)  \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
         end
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
-            if (PREG != 0)  \B.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
+            if (PREG != 0)  \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 2898 : 2608) ;
         end
         else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)  \B.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1718 : 1428) ;
+            if (PREG != 0)  \B.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1718 : 1428) ;
         end
     end
     endfunction
-    function integer \C.abc9_required ;
+    function integer \C.required ;
     begin
-        \C.abc9_required = 0;
-        if (CREG != 0)      \C.abc9_required =  168;
-        else if (PREG != 0) \C.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ;
+        \C.required = 0;
+        if (CREG != 0)      \C.required =  168;
+        else if (PREG != 0) \C.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1534 : 1244) ;
     end
     endfunction
-    function integer \D.abc9_required ;
+    function integer \D.required ;
     begin
-        \D.abc9_required = 0;
+        \D.required = 0;
         if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
         end
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
-            if (DREG != 0)       \D.abc9_required =  248;
-            else if (ADREG != 0) \D.abc9_required = 1195;
-            else if (MREG != 0)  \D.abc9_required = 2310;
-            else if (PREG != 0)  \D.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3925 : 3635) ;
+            if (DREG != 0)       \D.required =  248;
+            else if (ADREG != 0) \D.required = 1195;
+            else if (MREG != 0)  \D.required = 2310;
+            else if (PREG != 0)  \D.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 3925 : 3635) ;
         end
         else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
         end
     end
     endfunction
-    function integer \PCIN.abc9_required ;
+    function integer \PCIN.required ;
     begin
-        \PCIN.abc9_required = 0;
-        if (PREG != 0) \PCIN.abc9_required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025) ;
+        \PCIN.required = 0;
+        if (PREG != 0) \PCIN.required = (USE_PATTERN_DETECT != "NO_PATDET" ? 1315 : 1025) ;
     end
     endfunction
-    function integer \P.abc9_arrival ;
+    function integer \P.arrival ;
     begin
-        \P.abc9_arrival = 0;
+        \P.arrival = 0;
         if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)       \P.abc9_arrival =  329;
+            if (PREG != 0)       \P.arrival =  329;
             // Worst-case from CREG and MREG
-            else if (CREG != 0)  \P.abc9_arrival = 1687;
-            else if (MREG != 0)  \P.abc9_arrival = 1671;
+            else if (CREG != 0)  \P.arrival = 1687;
+            else if (MREG != 0)  \P.arrival = 1671;
             // Worst-case from AREG and BREG
-            else if (AREG != 0)  \P.abc9_arrival = 2952;
-            else if (BREG != 0)  \P.abc9_arrival = 2813;
+            else if (AREG != 0)  \P.arrival = 2952;
+            else if (BREG != 0)  \P.arrival = 2813;
         end
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
-            if (PREG != 0)       \P.abc9_arrival =  329;
+            if (PREG != 0)       \P.arrival =  329;
             // Worst-case from CREG and MREG
-            else if (CREG != 0)  \P.abc9_arrival = 1687;
-            else if (MREG != 0)  \P.abc9_arrival = 1671;
+            else if (CREG != 0)  \P.arrival = 1687;
+            else if (MREG != 0)  \P.arrival = 1671;
             // Worst-case from AREG, ADREG, BREG, DREG
-            else if (AREG != 0)  \P.abc9_arrival = 3935;
-            else if (DREG != 0)  \P.abc9_arrival = 3908;
-            else if (ADREG != 0) \P.abc9_arrival = 2958;
-            else if (BREG != 0)  \P.abc9_arrival = 2813;
+            else if (AREG != 0)  \P.arrival = 3935;
+            else if (DREG != 0)  \P.arrival = 3908;
+            else if (ADREG != 0) \P.arrival = 2958;
+            else if (BREG != 0)  \P.arrival = 2813;
         end
         else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)       \P.abc9_arrival =  329;
+            if (PREG != 0)       \P.arrival =  329;
             // Worst-case from AREG, BREG, CREG
-            else if (CREG != 0)  \P.abc9_arrival = 1687;
-            else if (AREG != 0)  \P.abc9_arrival = 1632;
-            else if (BREG != 0)  \P.abc9_arrival = 1616;
+            else if (CREG != 0)  \P.arrival = 1687;
+            else if (AREG != 0)  \P.arrival = 1632;
+            else if (BREG != 0)  \P.arrival = 1616;
         end
         //else
         //    $error("Invalid DSP48E1 configuration");
     end
     endfunction
-    function integer \PCOUT.abc9_arrival ;
+    function integer \PCOUT.arrival ;
     begin
-        \PCOUT.abc9_arrival = 0;
+        \PCOUT.arrival = 0;
         if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)       \PCOUT.abc9_arrival =  435;
+            if (PREG != 0)       \PCOUT.arrival =  435;
             // Worst-case from CREG and MREG
-            else if (CREG != 0)  \PCOUT.abc9_arrival = 1835;
-            else if (MREG != 0)  \PCOUT.abc9_arrival = 1819;
+            else if (CREG != 0)  \PCOUT.arrival = 1835;
+            else if (MREG != 0)  \PCOUT.arrival = 1819;
             // Worst-case from AREG and BREG
-            else if (AREG != 0)  \PCOUT.abc9_arrival = 3098;
-            else if (BREG != 0)  \PCOUT.abc9_arrival = 2960;
+            else if (AREG != 0)  \PCOUT.arrival = 3098;
+            else if (BREG != 0)  \PCOUT.arrival = 2960;
         end
         else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
-            if (PREG != 0)       \PCOUT.abc9_arrival =  435;
+            if (PREG != 0)       \PCOUT.arrival =  435;
             // Worst-case from CREG and MREG
-            else if (CREG != 0)  \PCOUT.abc9_arrival = 1835;
-            else if (MREG != 0)  \PCOUT.abc9_arrival = 1819;
+            else if (CREG != 0)  \PCOUT.arrival = 1835;
+            else if (MREG != 0)  \PCOUT.arrival = 1819;
             // Worst-case from AREG, ADREG, BREG, DREG
-            else if (AREG != 0)  \PCOUT.abc9_arrival = 4083;
-            else if (DREG != 0)  \PCOUT.abc9_arrival = 4056;
-            else if (BREG != 0)  \PCOUT.abc9_arrival = 2960;
-            else if (ADREG != 0) \PCOUT.abc9_arrival = 2859;
+            else if (AREG != 0)  \PCOUT.arrival = 4083;
+            else if (DREG != 0)  \PCOUT.arrival = 4056;
+            else if (BREG != 0)  \PCOUT.arrival = 2960;
+            else if (ADREG != 0) \PCOUT.arrival = 2859;
         end
         else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
-            if (PREG != 0)       \PCOUT.abc9_arrival =  435;
+            if (PREG != 0)       \PCOUT.arrival =  435;
             // Worst-case from AREG, BREG, CREG
-            else if (CREG != 0)  \PCOUT.abc9_arrival = 1835;
-            else if (AREG != 0)  \PCOUT.abc9_arrival = 1780;
-            else if (BREG != 0)  \PCOUT.abc9_arrival = 1765;
+            else if (CREG != 0)  \PCOUT.arrival = 1835;
+            else if (AREG != 0)  \PCOUT.arrival = 1780;
+            else if (BREG != 0)  \PCOUT.arrival = 1765;
         end
         //else
         //    $error("Invalid DSP48E1 configuration");
@@ -3192,20 +3192,20 @@ module DSP48E1 (
     endfunction
 
     specify
-        $setup(A   , posedge CLK &&& !IS_CLK_INVERTED, \A.abc9_required () );
-        $setup(A   , negedge CLK &&&  IS_CLK_INVERTED, \A.abc9_required () );
-        $setup(B   , posedge CLK &&& !IS_CLK_INVERTED, \B.abc9_required () );
-        $setup(B   , negedge CLK &&&  IS_CLK_INVERTED, \B.abc9_required () );
-        $setup(C   , posedge CLK &&& !IS_CLK_INVERTED, \C.abc9_required () );
-        $setup(C   , negedge CLK &&&  IS_CLK_INVERTED, \C.abc9_required () );
-        $setup(D   , posedge CLK &&& !IS_CLK_INVERTED, \D.abc9_required () );
-        $setup(D   , negedge CLK &&&  IS_CLK_INVERTED, \D.abc9_required () );
-        $setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, \PCIN.abc9_required () );
-        $setup(PCIN, negedge CLK &&&  IS_CLK_INVERTED, \PCIN.abc9_required () );
-        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.abc9_arrival () ;
-        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.abc9_arrival () ;
-        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.abc9_arrival () ;
-        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.abc9_arrival () ;
+        $setup(A   , posedge CLK &&& !IS_CLK_INVERTED, \A.required () );
+        $setup(A   , negedge CLK &&&  IS_CLK_INVERTED, \A.required () );
+        $setup(B   , posedge CLK &&& !IS_CLK_INVERTED, \B.required () );
+        $setup(B   , negedge CLK &&&  IS_CLK_INVERTED, \B.required () );
+        $setup(C   , posedge CLK &&& !IS_CLK_INVERTED, \C.required () );
+        $setup(C   , negedge CLK &&&  IS_CLK_INVERTED, \C.required () );
+        $setup(D   , posedge CLK &&& !IS_CLK_INVERTED, \D.required () );
+        $setup(D   , negedge CLK &&&  IS_CLK_INVERTED, \D.required () );
+        $setup(PCIN, posedge CLK &&& !IS_CLK_INVERTED, \PCIN.required () );
+        $setup(PCIN, negedge CLK &&&  IS_CLK_INVERTED, \PCIN.required () );
+        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (P : 48'bx)) = \P.arrival () ;
+        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (P : 48'bx)) = \P.arrival () ;
+        if (!IS_CLK_INVERTED && CEP) (posedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
+        if ( IS_CLK_INVERTED && CEP) (negedge CLK => (PCOUT : 48'bx)) = \PCOUT.arrival () ;
     endspecify
 `endif
 
@@ -3591,3 +3591,415 @@ module DSP48E1 (
 endmodule
 
 // TODO: DSP48E2 (Ultrascale).
+
+// Block RAM
+
+module RAMB18E1 (...);
+    parameter integer DOA_REG = 0;
+    parameter integer DOB_REG = 0;
+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_A = 18'h0;
+    parameter INIT_B = 18'h0;
+    parameter INIT_FILE = "NONE";
+    parameter RAM_MODE = "TDP";
+    parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
+    parameter integer READ_WIDTH_A = 0;
+    parameter integer READ_WIDTH_B = 0;
+    parameter RSTREG_PRIORITY_A = "RSTREG";
+    parameter RSTREG_PRIORITY_B = "RSTREG";
+    parameter SIM_COLLISION_CHECK = "ALL";
+    parameter SIM_DEVICE = "VIRTEX6";
+    parameter SRVAL_A = 18'h0;
+    parameter SRVAL_B = 18'h0;
+    parameter WRITE_MODE_A = "WRITE_FIRST";
+    parameter WRITE_MODE_B = "WRITE_FIRST";
+    parameter integer WRITE_WIDTH_A = 0;
+    parameter integer WRITE_WIDTH_B = 0;
+    parameter IS_CLKARDCLK_INVERTED = 1'b0;
+    parameter IS_CLKBWRCLK_INVERTED = 1'b0;
+    parameter IS_ENARDEN_INVERTED = 1'b0;
+    parameter IS_ENBWREN_INVERTED = 1'b0;
+    parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
+    parameter IS_RSTRAMB_INVERTED = 1'b0;
+    parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
+    parameter IS_RSTREGB_INVERTED = 1'b0;
+    output [15:0] DOADO;
+    output [15:0] DOBDO;
+    output [1:0] DOPADOP;
+    output [1:0] DOPBDOP;
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
+    input CLKARDCLK;
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
+    input CLKBWRCLK;
+    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
+    input ENARDEN;
+    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
+    input ENBWREN;
+    input REGCEAREGCE;
+    input REGCEB;
+    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
+    input RSTRAMARSTRAM;
+    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
+    input RSTRAMB;
+    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
+    input RSTREGARSTREG;
+    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
+    input RSTREGB;
+    input [13:0] ADDRARDADDR;
+    input [13:0] ADDRBWRADDR;
+    input [15:0] DIADI;
+    input [15:0] DIBDI;
+    input [1:0] DIPADIP;
+    input [1:0] DIPBDIP;
+    input [1:0] WEA;
+    input [3:0] WEBWE;
+
+    specify
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
+        $setup(ADDRARDADDR, posedge CLKARDCLK, 566);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
+        $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
+        $setup(WEA, posedge CLKARDCLK, 532);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
+        $setup(WEBWE, posedge CLKBWRCLK, 532);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
+        $setup(DIADI, posedge CLKARDCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
+        $setup(DIBDI, posedge CLKBWRCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
+        $setup(DIPADIP, posedge CLKARDCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
+        $setup(DIPBDIP, posedge CLKBWRCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
+        (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
+        (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
+        (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
+        (posedge CLKARDCLK => (DOPBDOP : 2'bx)) = 2454;
+    endspecify
+endmodule
+
+module RAMB36E1 (...);
+    parameter integer DOA_REG = 0;
+    parameter integer DOB_REG = 0;
+    parameter EN_ECC_READ = "FALSE";
+    parameter EN_ECC_WRITE = "FALSE";
+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_A = 36'h0;
+    parameter INIT_B = 36'h0;
+    parameter INIT_FILE = "NONE";
+    parameter RAM_EXTENSION_A = "NONE";
+    parameter RAM_EXTENSION_B = "NONE";
+    parameter RAM_MODE = "TDP";
+    parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
+    parameter integer READ_WIDTH_A = 0;
+    parameter integer READ_WIDTH_B = 0;
+    parameter RSTREG_PRIORITY_A = "RSTREG";
+    parameter RSTREG_PRIORITY_B = "RSTREG";
+    parameter SIM_COLLISION_CHECK = "ALL";
+    parameter SIM_DEVICE = "VIRTEX6";
+    parameter SRVAL_A = 36'h0;
+    parameter SRVAL_B = 36'h0;
+    parameter WRITE_MODE_A = "WRITE_FIRST";
+    parameter WRITE_MODE_B = "WRITE_FIRST";
+    parameter integer WRITE_WIDTH_A = 0;
+    parameter integer WRITE_WIDTH_B = 0;
+    parameter IS_CLKARDCLK_INVERTED = 1'b0;
+    parameter IS_CLKBWRCLK_INVERTED = 1'b0;
+    parameter IS_ENARDEN_INVERTED = 1'b0;
+    parameter IS_ENBWREN_INVERTED = 1'b0;
+    parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
+    parameter IS_RSTRAMB_INVERTED = 1'b0;
+    parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
+    parameter IS_RSTREGB_INVERTED = 1'b0;
+    output CASCADEOUTA;
+    output CASCADEOUTB;
+    output [31:0] DOADO;
+    output [31:0] DOBDO;
+    output [3:0] DOPADOP;
+    output [3:0] DOPBDOP;
+    output [7:0] ECCPARITY;
+    output [8:0] RDADDRECC;
+    output SBITERR;
+    output DBITERR;
+    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
+    input ENARDEN;
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
+    input CLKARDCLK;
+    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
+    input RSTRAMARSTRAM;
+    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
+    input RSTREGARSTREG;
+    input CASCADEINA;
+    input REGCEAREGCE;
+    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
+    input ENBWREN;
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
+    input CLKBWRCLK;
+    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
+    input RSTRAMB;
+    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
+    input RSTREGB;
+    input CASCADEINB;
+    input REGCEB;
+    input INJECTDBITERR;
+    input INJECTSBITERR;
+    input [15:0] ADDRARDADDR;
+    input [15:0] ADDRBWRADDR;
+    input [31:0] DIADI;
+    input [31:0] DIBDI;
+    input [3:0] DIPADIP;
+    input [3:0] DIPBDIP;
+    input [3:0] WEA;
+    input [7:0] WEBWE;
+
+    specify
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
+        $setup(ADDRARDADDR, posedge CLKARDCLK, 566);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
+        $setup(ADDRBWRADDR, posedge CLKBWRCLK, 566);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
+        $setup(WEA, posedge CLKARDCLK, 532);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
+        $setup(WEBWE, posedge CLKBWRCLK, 532);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
+        $setup(DIADI, posedge CLKARDCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
+        $setup(DIBDI, posedge CLKBWRCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
+        $setup(DIPADIP, posedge CLKARDCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
+        $setup(DIPBDIP, posedge CLKBWRCLK, 737);
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
+        (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
+        (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
+        (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
+        (posedge CLKARDCLK => (DOPBDOP : 4'bx)) = 2454;
+    endspecify
+endmodule
+
+
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index 631664d67..ca301685b 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -144,23 +144,9 @@ CELLS = [
     Cell('RAMB16BWE_S36_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
     Cell('RAMB16BWE_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
     # Spartan 3A DSP.
-    Cell('RAMB16BWER', port_attrs={
-        'CLKA': ['clkbuf_sink'],
-        'CLKB': ['clkbuf_sink'],
-        #'DOA': ['abc9_arrival=<TODO>'],
-        #'DOB': ['abc9_arrival=<TODO>'],
-        #'DOPA': ['abc9_arrival=<TODO>'],
-        #'DOPB': ['abc9_arrival=<TODO>'],
-    }),
+    Cell('RAMB16BWER', port_attrs={ 'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
     # Spartan 6 (in addition to above).
-    Cell('RAMB8BWER', port_attrs={
-        'CLKAWRCLK': ['clkbuf_sink'],
-        'CLKBRDCLK': ['clkbuf_sink'],
-        #'DOADO': ['abc9_arrival=<TODO>'],
-        #'DOBDO': ['abc9_arrival=<TODO>'],
-        #'DOPADOP': ['abc9_arrival=<TODO>'],
-        #'DOPBDOP': ['abc9_arrival=<TODO>'],
-    }),
+    Cell('RAMB8BWER', port_attrs={ 'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}),
     # Virtex 4.
     Cell('FIFO16', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     Cell('RAMB16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}),
@@ -177,62 +163,8 @@ CELLS = [
     # Virtex 6 / Series 7.
     Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
-    Cell('RAMB18E1', port_attrs={
-        'CLKARDCLK': ['clkbuf_sink'],
-        'CLKBWRCLK': ['clkbuf_sink'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
-        'DOADO': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
-        'DOBDO': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
-        'DOPADOP': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
-        'DOPBDOP': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
-        'ADDRARDADDR': ['abc9_required=566'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
-        'ADDRBWRADDR': ['abc9_required=566'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
-        'WEA': ['abc9_required=532'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
-        'WEBWE': ['abc9_required=532'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
-        'DIADI': ['abc9_required=737'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
-        'DIBDI': ['abc9_required=737'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
-        'DIPADIP': ['abc9_required=737'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
-        'DIPBDIP': ['abc9_required=737'],
-    }),
-    Cell('RAMB36E1', port_attrs={
-        'CLKARDCLK': ['clkbuf_sink'],
-        'CLKBWRCLK': ['clkbuf_sink'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
-        'DOADO': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
-        'DOBDO': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
-        'DOPADOP': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
-        'DOPBDOP': ['abc9_arrival=2454'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
-        'ADDRARDADDR': ['abc9_required=566'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L17
-        'ADDRBWRADDR': ['abc9_required=566'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L19
-        'WEA': ['abc9_required=532'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
-        'WEBWE': ['abc9_required=532'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
-        'DIADI': ['abc9_required=737'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
-        'DIBDI': ['abc9_required=737'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L125
-        'DIPADIP': ['abc9_required=737'],
-        # https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
-        'DIPBDIP': ['abc9_required=737'],
-    }),
+    Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
+    Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
     # Ultrascale.
     Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index a779bcae0..ac4ad4e36 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -4390,384 +4390,6 @@ module FIFO36E1 (...);
     input WREN;
 endmodule
 
-module RAMB18E1 (...);
-    parameter integer DOA_REG = 0;
-    parameter integer DOB_REG = 0;
-    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_A = 18'h0;
-    parameter INIT_B = 18'h0;
-    parameter INIT_FILE = "NONE";
-    parameter RAM_MODE = "TDP";
-    parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
-    parameter integer READ_WIDTH_A = 0;
-    parameter integer READ_WIDTH_B = 0;
-    parameter RSTREG_PRIORITY_A = "RSTREG";
-    parameter RSTREG_PRIORITY_B = "RSTREG";
-    parameter SIM_COLLISION_CHECK = "ALL";
-    parameter SIM_DEVICE = "VIRTEX6";
-    parameter SRVAL_A = 18'h0;
-    parameter SRVAL_B = 18'h0;
-    parameter WRITE_MODE_A = "WRITE_FIRST";
-    parameter WRITE_MODE_B = "WRITE_FIRST";
-    parameter integer WRITE_WIDTH_A = 0;
-    parameter integer WRITE_WIDTH_B = 0;
-    parameter IS_CLKARDCLK_INVERTED = 1'b0;
-    parameter IS_CLKBWRCLK_INVERTED = 1'b0;
-    parameter IS_ENARDEN_INVERTED = 1'b0;
-    parameter IS_ENBWREN_INVERTED = 1'b0;
-    parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
-    parameter IS_RSTRAMB_INVERTED = 1'b0;
-    parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
-    parameter IS_RSTREGB_INVERTED = 1'b0;
-    (* abc9_arrival=2454 *)
-    output [15:0] DOADO;
-    (* abc9_arrival=2454 *)
-    output [15:0] DOBDO;
-    (* abc9_arrival=2454 *)
-    output [1:0] DOPADOP;
-    (* abc9_arrival=2454 *)
-    output [1:0] DOPBDOP;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
-    input CLKARDCLK;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
-    input CLKBWRCLK;
-    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
-    input ENARDEN;
-    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
-    input ENBWREN;
-    input REGCEAREGCE;
-    input REGCEB;
-    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
-    input RSTRAMARSTRAM;
-    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
-    input RSTRAMB;
-    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
-    input RSTREGARSTREG;
-    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
-    input RSTREGB;
-    (* abc9_required=566 *)
-    input [13:0] ADDRARDADDR;
-    (* abc9_required=566 *)
-    input [13:0] ADDRBWRADDR;
-    (* abc9_required=737 *)
-    input [15:0] DIADI;
-    (* abc9_required=737 *)
-    input [15:0] DIBDI;
-    (* abc9_required=737 *)
-    input [1:0] DIPADIP;
-    (* abc9_required=737 *)
-    input [1:0] DIPBDIP;
-    (* abc9_required=532 *)
-    input [1:0] WEA;
-    (* abc9_required=532 *)
-    input [3:0] WEBWE;
-endmodule
-
-module RAMB36E1 (...);
-    parameter integer DOA_REG = 0;
-    parameter integer DOB_REG = 0;
-    parameter EN_ECC_READ = "FALSE";
-    parameter EN_ECC_WRITE = "FALSE";
-    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
-    parameter INIT_A = 36'h0;
-    parameter INIT_B = 36'h0;
-    parameter INIT_FILE = "NONE";
-    parameter RAM_EXTENSION_A = "NONE";
-    parameter RAM_EXTENSION_B = "NONE";
-    parameter RAM_MODE = "TDP";
-    parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE";
-    parameter integer READ_WIDTH_A = 0;
-    parameter integer READ_WIDTH_B = 0;
-    parameter RSTREG_PRIORITY_A = "RSTREG";
-    parameter RSTREG_PRIORITY_B = "RSTREG";
-    parameter SIM_COLLISION_CHECK = "ALL";
-    parameter SIM_DEVICE = "VIRTEX6";
-    parameter SRVAL_A = 36'h0;
-    parameter SRVAL_B = 36'h0;
-    parameter WRITE_MODE_A = "WRITE_FIRST";
-    parameter WRITE_MODE_B = "WRITE_FIRST";
-    parameter integer WRITE_WIDTH_A = 0;
-    parameter integer WRITE_WIDTH_B = 0;
-    parameter IS_CLKARDCLK_INVERTED = 1'b0;
-    parameter IS_CLKBWRCLK_INVERTED = 1'b0;
-    parameter IS_ENARDEN_INVERTED = 1'b0;
-    parameter IS_ENBWREN_INVERTED = 1'b0;
-    parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
-    parameter IS_RSTRAMB_INVERTED = 1'b0;
-    parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
-    parameter IS_RSTREGB_INVERTED = 1'b0;
-    output CASCADEOUTA;
-    output CASCADEOUTB;
-    (* abc9_arrival=2454 *)
-    output [31:0] DOADO;
-    (* abc9_arrival=2454 *)
-    output [31:0] DOBDO;
-    (* abc9_arrival=2454 *)
-    output [3:0] DOPADOP;
-    (* abc9_arrival=2454 *)
-    output [3:0] DOPBDOP;
-    output [7:0] ECCPARITY;
-    output [8:0] RDADDRECC;
-    output SBITERR;
-    output DBITERR;
-    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
-    input ENARDEN;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
-    input CLKARDCLK;
-    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
-    input RSTRAMARSTRAM;
-    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
-    input RSTREGARSTREG;
-    input CASCADEINA;
-    input REGCEAREGCE;
-    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
-    input ENBWREN;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
-    input CLKBWRCLK;
-    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
-    input RSTRAMB;
-    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
-    input RSTREGB;
-    input CASCADEINB;
-    input REGCEB;
-    input INJECTDBITERR;
-    input INJECTSBITERR;
-    (* abc9_required=566 *)
-    input [15:0] ADDRARDADDR;
-    (* abc9_required=566 *)
-    input [15:0] ADDRBWRADDR;
-    (* abc9_required=737 *)
-    input [31:0] DIADI;
-    (* abc9_required=737 *)
-    input [31:0] DIBDI;
-    (* abc9_required=737 *)
-    input [3:0] DIPADIP;
-    (* abc9_required=737 *)
-    input [3:0] DIPBDIP;
-    (* abc9_required=532 *)
-    input [3:0] WEA;
-    (* abc9_required=532 *)
-    input [7:0] WEBWE;
-endmodule
-
 module FIFO18E2 (...);
     parameter CASCADE_ORDER = "NONE";
     parameter CLOCK_DOMAINS = "INDEPENDENT";

From 683c5ce9409b578df518df829b76777ab69cf87b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 13:26:00 -0800
Subject: [PATCH 28/46] abc9_ops: demote lack of box timing info to warning

---
 passes/techmap/abc9_ops.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index dad39828a..fc2f52157 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -669,8 +669,10 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		ss << std::endl;
 
 		auto &t = timing.setup_module(module).comb;
-		if (t.empty())
-			log_error("(* abc9_box *) module '%s' has no timing information.\n", log_id(module));
+		if (t.empty()) {
+			log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
+			continue;
+		}
 
 		for (const auto &o : outputs) {
 			first = true;

From 5ff60d2057992bdc9f0ff04eee78d7bf6be0ee44 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 13:43:34 -0800
Subject: [PATCH 29/46] write_xaiger: add comment about arrival times of flop
 outputs

---
 backends/aiger/xaiger.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 2a39d225d..dc0f997fe 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -656,6 +656,7 @@ struct XAigerWriter
 					write_s_buffer(0);
 				}
 
+				// Use arrival time from output of flop box
 				write_i_buffer(arrival_times.at(d, 0));
 				//write_o_buffer(0);
 			}

From d6cff777513ff5b470bcd37588c123e118ad0cdb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 13:53:28 -0800
Subject: [PATCH 30/46] abc9_ops: still emit delay table even box has no timing

---
 passes/techmap/abc9_ops.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index fc2f52157..8337b61b1 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -669,10 +669,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		ss << std::endl;
 
 		auto &t = timing.setup_module(module).comb;
-		if (t.empty()) {
+		if (t.empty())
 			log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
-			continue;
-		}
 
 		for (const auto &o : outputs) {
 			first = true;

From b0ffd9cd8b13ece876519c2c3e9b063635610e3c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Feb 2020 18:56:10 -0800
Subject: [PATCH 31/46] Make +/xilinx/cells_sim.v legal

---
 techlibs/xilinx/cells_sim.v | 154 ++++++++++++++++++------------------
 1 file changed, 78 insertions(+), 76 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 016324774..0896f3176 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -3594,7 +3594,40 @@ endmodule
 
 // Block RAM
 
-module RAMB18E1 (...);
+module RAMB18E1 (
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
+    input CLKARDCLK,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
+    input CLKBWRCLK,
+    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
+    input ENARDEN,
+    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
+    input ENBWREN,
+    input REGCEAREGCE,
+    input REGCEB,
+    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
+    input RSTRAMARSTRAM,
+    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
+    input RSTRAMB,
+    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
+    input RSTREGARSTREG,
+    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
+    input RSTREGB,
+    input [13:0] ADDRARDADDR,
+    input [13:0] ADDRBWRADDR,
+    input [15:0] DIADI,
+    input [15:0] DIBDI,
+    input [1:0] DIPADIP,
+    input [1:0] DIPBDIP,
+    input [1:0] WEA,
+    input [3:0] WEBWE,
+    output [15:0] DOADO,
+    output [15:0] DOBDO,
+    output [1:0] DOPADOP,
+    output [1:0] DOPBDOP
+);
     parameter integer DOA_REG = 0;
     parameter integer DOB_REG = 0;
     parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
@@ -3694,38 +3727,6 @@ module RAMB18E1 (...);
     parameter IS_RSTRAMB_INVERTED = 1'b0;
     parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
     parameter IS_RSTREGB_INVERTED = 1'b0;
-    output [15:0] DOADO;
-    output [15:0] DOBDO;
-    output [1:0] DOPADOP;
-    output [1:0] DOPBDOP;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
-    input CLKARDCLK;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
-    input CLKBWRCLK;
-    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
-    input ENARDEN;
-    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
-    input ENBWREN;
-    input REGCEAREGCE;
-    input REGCEB;
-    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
-    input RSTRAMARSTRAM;
-    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
-    input RSTRAMB;
-    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
-    input RSTREGARSTREG;
-    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
-    input RSTREGB;
-    input [13:0] ADDRARDADDR;
-    input [13:0] ADDRBWRADDR;
-    input [15:0] DIADI;
-    input [15:0] DIBDI;
-    input [1:0] DIPADIP;
-    input [1:0] DIPBDIP;
-    input [1:0] WEA;
-    input [3:0] WEBWE;
 
     specify
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13
@@ -3755,7 +3756,50 @@ module RAMB18E1 (...);
     endspecify
 endmodule
 
-module RAMB36E1 (...);
+module RAMB36E1 (
+    output CASCADEOUTA,
+    output CASCADEOUTB,
+    output [31:0] DOADO,
+    output [31:0] DOBDO,
+    output [3:0] DOPADOP,
+    output [3:0] DOPBDOP,
+    output [7:0] ECCPARITY,
+    output [8:0] RDADDRECC,
+    output SBITERR,
+    output DBITERR,
+    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
+    input ENARDEN,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
+    input CLKARDCLK,
+    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
+    input RSTRAMARSTRAM,
+    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
+    input RSTREGARSTREG,
+    input CASCADEINA,
+    input REGCEAREGCE,
+    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
+    input ENBWREN,
+    (* clkbuf_sink *)
+    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
+    input CLKBWRCLK,
+    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
+    input RSTRAMB,
+    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
+    input RSTREGB,
+    input CASCADEINB,
+    input REGCEB,
+    input INJECTDBITERR,
+    input INJECTSBITERR,
+    input [15:0] ADDRARDADDR,
+    input [15:0] ADDRBWRADDR,
+    input [31:0] DIADI,
+    input [31:0] DIBDI,
+    input [3:0] DIPADIP,
+    input [3:0] DIPBDIP,
+    input [3:0] WEA,
+    input [7:0] WEBWE
+);
     parameter integer DOA_REG = 0;
     parameter integer DOB_REG = 0;
     parameter EN_ECC_READ = "FALSE";
@@ -3931,48 +3975,6 @@ module RAMB36E1 (...);
     parameter IS_RSTRAMB_INVERTED = 1'b0;
     parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
     parameter IS_RSTREGB_INVERTED = 1'b0;
-    output CASCADEOUTA;
-    output CASCADEOUTB;
-    output [31:0] DOADO;
-    output [31:0] DOBDO;
-    output [3:0] DOPADOP;
-    output [3:0] DOPBDOP;
-    output [7:0] ECCPARITY;
-    output [8:0] RDADDRECC;
-    output SBITERR;
-    output DBITERR;
-    (* invertible_pin = "IS_ENARDEN_INVERTED" *)
-    input ENARDEN;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKARDCLK_INVERTED" *)
-    input CLKARDCLK;
-    (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *)
-    input RSTRAMARSTRAM;
-    (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *)
-    input RSTREGARSTREG;
-    input CASCADEINA;
-    input REGCEAREGCE;
-    (* invertible_pin = "IS_ENBWREN_INVERTED" *)
-    input ENBWREN;
-    (* clkbuf_sink *)
-    (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *)
-    input CLKBWRCLK;
-    (* invertible_pin = "IS_RSTRAMB_INVERTED" *)
-    input RSTRAMB;
-    (* invertible_pin = "IS_RSTREGB_INVERTED" *)
-    input RSTREGB;
-    input CASCADEINB;
-    input REGCEB;
-    input INJECTDBITERR;
-    input INJECTSBITERR;
-    input [15:0] ADDRARDADDR;
-    input [15:0] ADDRBWRADDR;
-    input [31:0] DIADI;
-    input [31:0] DIBDI;
-    input [3:0] DIPADIP;
-    input [3:0] DIPBDIP;
-    input [3:0] WEA;
-    input [7:0] WEBWE;
 
     specify
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L13

From 717fb492b35a93ae78e33f742d8c3d493be7e4e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Feb 2020 08:27:41 -0800
Subject: [PATCH 32/46] Update bug1630.ys to use -lut 4 instead of lut file

---
 tests/arch/ecp5/bug1630.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys
index b419fb9bb..63df1ad5b 100644
--- a/tests/arch/ecp5/bug1630.ys
+++ b/tests/arch/ecp5/bug1630.ys
@@ -1,2 +1,2 @@
 read_ilang bug1630.il.gz
-abc9 -lut +/ecp5/abc9_5g.lut
+abc9 -lut 4

From f858219c4ed18fb5886641efd1e71f5aad0b1c84 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Feb 2020 08:29:10 -0800
Subject: [PATCH 33/46] Cleanup tests

---
 tests/{various => arch/xilinx}/bug1480.ys | 0
 tests/various/pmux2shiftx.v               | 2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename tests/{various => arch/xilinx}/bug1480.ys (100%)

diff --git a/tests/various/bug1480.ys b/tests/arch/xilinx/bug1480.ys
similarity index 100%
rename from tests/various/bug1480.ys
rename to tests/arch/xilinx/bug1480.ys
diff --git a/tests/various/pmux2shiftx.v b/tests/various/pmux2shiftx.v
index 563394080..c1994e92c 100644
--- a/tests/various/pmux2shiftx.v
+++ b/tests/various/pmux2shiftx.v
@@ -33,7 +33,7 @@ module pmux2shiftx_test (
 	end
 endmodule
 
-module issue01135(input [7:0] i, output o);
+module issue01135(input [7:0] i, output reg o);
 always @*
 case (i[6:3])
     4: o <= i[0];

From aa969f87784cda995d4d7650f0a8050ef555ff62 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 15 Feb 2020 09:13:21 -0800
Subject: [PATCH 34/46] More +/ice40/cells_sim.v fixes

---
 techlibs/ice40/cells_sim.v | 54 +++++++++++++++++++-------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 0b7fdd2a9..f9f8c9e66 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1767,67 +1767,67 @@ module SB_RAM40_4KNRNW (
 `ifdef ICE40_HX
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L343-L358
-		$setup(MASK, negedge WCLK &&& WE && WCLKE, 274);
+		$setup(MASK, posedge WCLKN &&& WE && WCLKE, 274);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L359-L369
-		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 203);
+		$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 203);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L370
-		$setup(RCLKE, negedge RCLK, 267);
+		$setup(RCLKE, posedge RCLKN, 267);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L371
-		$setup(RE, negedge RCLK, 98);
+		$setup(RE, posedge RCLKN, 98);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L372-L382
-		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 224);
+		$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 224);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L383
-		$setup(WCLKE, negedge WCLK, 267);
+		$setup(WCLKE, posedge WCLKN, 267);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L384-L399
-		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 161);
+		$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 161);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400
-		$setup(WE, negedge WCLK, 133);
+		$setup(WE, posedge WCLKN, 133);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
-		(negedge RCLK => (RDATA : 16'bx)) = 2146;
+		(posedge RCLKN => (RDATA : 16'bx)) = 2146;
 	endspecify
 `endif
 `ifdef ICE40_LP
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L343-L358
-		$setup(MASK, negedge WCLK &&& WE && WCLKE, 403);
+		$setup(MASK, posedge WCLKN &&& WE && WCLKE, 403);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L359-L369
-		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 300);
+		$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 300);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L370
-		$setup(RCLKE, negedge RCLK, 393);
+		$setup(RCLKE, posedge RCLKN, 393);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L371
-		$setup(RE, negedge RCLK, 145);
+		$setup(RE, posedge RCLKN, 145);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L372-L382
-		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 331);
+		$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 331);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L383
-		$setup(WCLKE, negedge WCLK, 393);
+		$setup(WCLKE, posedge WCLKN, 393);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L384-L399
-		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 238);
+		$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 238);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400
-		$setup(WE, negedge WCLK, 196);
+		$setup(WE, posedge WCLKN, 196);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
-		(negedge RCLK => (RDATA : 16'bx)) = 3163;
+		(posedge RCLKN => (RDATA : 16'bx)) = 3163;
 	endspecify
 `endif
 `ifdef ICE40_U
 	specify
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12968-12983
-		$setup(MASK, negedge WCLK &&& WE && WCLKE, 517);
+		$setup(MASK, posedge WCLKN &&& WE && WCLKE, 517);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12984-12994
-		$setup(RADDR, negedge RCLK &&& RE && RCLKE, 384);
+		$setup(RADDR, posedge RCLKN &&& RE && RCLKE, 384);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12995
-		$setup(RCLKE, negedge RCLK, 503);
+		$setup(RCLKE, posedge RCLKN, 503);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12996
-		$setup(RE, negedge RCLK, 185);
+		$setup(RE, posedge RCLKN, 185);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L12997-13007
-		$setup(WADDR, negedge WCLK &&& WE && WCLKE, 424);
+		$setup(WADDR, posedge WCLKN &&& WE && WCLKE, 424);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13008
-		$setup(WCLKE, negedge WCLK, 503);
+		$setup(WCLKE, posedge WCLKN, 503);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13009-13024
-		$setup(WDATA, negedge WCLK &&& WE && WCLKE, 305);
+		$setup(WDATA, posedge WCLKN &&& WE && WCLKE, 305);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025
-		$setup(WE, negedge WCLK, 252);
+		$setup(WE, posedge WCLKN, 252);
 		// https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
-		(negedge RCLK => (RDATA : 16'bx)) = 1179;
+		(posedge RCLKN => (RDATA : 16'bx)) = 1179;
 	endspecify
 `endif
 endmodule

From 7c3b4b80ea62c53e3f4bd6d91dcf02ef09c40da7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 08:30:41 -0800
Subject: [PATCH 35/46] Fix spacing

---
 kernel/timinginfo.h        | 100 ++++++++++++++++++-------------------
 passes/techmap/abc9_ops.cc |  36 ++++++-------
 2 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 9256c6445..e2af4d51a 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -36,7 +36,7 @@ struct ModuleTiming
 
 struct TimingInfo
 {
-        dict<RTLIL::IdString, ModuleTiming> data;
+	dict<RTLIL::IdString, ModuleTiming> data;
 
 	TimingInfo()
 	{
@@ -53,52 +53,52 @@ struct TimingInfo
 			if (!module->get_blackbox_attribute())
 				continue;
 			setup_module(module);
-                }
+		}
 	}
 
 	const ModuleTiming& setup_module(RTLIL::Module *module)
 	{
-                auto r = data.insert(module->name);
-                log_assert(r.second);
-                auto &t = r.first->second;
+		auto r = data.insert(module->name);
+		log_assert(r.second);
+		auto &t = r.first->second;
 
 		for (auto cell : module->cells()) {
-                        if (cell->type == ID($specify2)) {
-                                auto src = cell->getPort(ID(SRC));
-                                auto dst = cell->getPort(ID(DST));
-                                for (const auto &c : src.chunks())
-                                        if (!c.wire->port_input)
-                                                log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
-                                for (const auto &c : dst.chunks())
-                                        if (!c.wire->port_output)
-                                                log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-                                int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
-                                int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
-                                int max = std::max(rise_max,fall_max);
-                                if (max < 0)
-                                        log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
-                                if (cell->getParam(ID(FULL)).as_bool()) {
-                                        for (const auto &s : src)
-                                                for (const auto &d : dst) {
-                                                        auto r = t.comb.insert(BitBit(s,d));
-                                                        if (!r.second)
-                                                                log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
-                                                        r.first->second = max;
-                                                }
-                                }
-                                else {
-                                        log_assert(GetSize(src) == GetSize(dst));
-                                        for (auto i = 0; i < GetSize(src); i++) {
-                                                const auto &s = src[i];
-                                                const auto &d = dst[i];
-                                                auto r = t.comb.insert(BitBit(s,d));
-                                                if (!r.second)
-                                                        log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
-                                                r.first->second = max;
-                                        }
-                                }
-                        }
-                        else if (cell->type == ID($specify3)) {
+			if (cell->type == ID($specify2)) {
+				auto src = cell->getPort(ID(SRC));
+				auto dst = cell->getPort(ID(DST));
+				for (const auto &c : src.chunks())
+					if (!c.wire->port_input)
+						log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
+				for (const auto &c : dst.chunks())
+					if (!c.wire->port_output)
+						log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
+				int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
+				int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+				int max = std::max(rise_max,fall_max);
+				if (max < 0)
+					log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
+				if (cell->getParam(ID(FULL)).as_bool()) {
+					for (const auto &s : src)
+						for (const auto &d : dst) {
+							auto r = t.comb.insert(BitBit(s,d));
+							if (!r.second)
+								log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
+							r.first->second = max;
+						}
+				}
+				else {
+					log_assert(GetSize(src) == GetSize(dst));
+					for (auto i = 0; i < GetSize(src); i++) {
+						const auto &s = src[i];
+						const auto &d = dst[i];
+						auto r = t.comb.insert(BitBit(s,d));
+						if (!r.second)
+							log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(s), log_signal(d));
+						r.first->second = max;
+					}
+				}
+			}
+			else if (cell->type == ID($specify3)) {
 				auto src = cell->getPort(ID(SRC));
 				auto dst = cell->getPort(ID(DST));
 				for (const auto &c : src.chunks())
@@ -117,9 +117,9 @@ struct TimingInfo
 					continue;
 				}
 				for (const auto &d : dst) {
-                                        auto &v = t.arrival[d];
+					auto &v = t.arrival[d];
 					v = std::max(v, max);
-                                }
+				}
 			}
 			else if (cell->type == ID($specrule)) {
 				auto type = cell->getParam(ID(TYPE)).decode_string();
@@ -141,19 +141,19 @@ struct TimingInfo
 					continue;
 				}
 				for (const auto &s : src) {
-                                        auto &v = t.required[s];
+					auto &v = t.required[s];
 					v = std::max(v, max);
-                                }
+				}
 			}
 		}
 
-                return t;
+		return t;
 	}
 
-        decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
-        decltype(data)::const_iterator end() const { return data.end(); }
-        int count(RTLIL::IdString module_name) const { return data.count(module_name); }
-        const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
+	decltype(data)::const_iterator find(RTLIL::IdString module_name) const { return data.find(module_name); }
+	decltype(data)::const_iterator end() const { return data.end(); }
+	int count(RTLIL::IdString module_name) const { return data.count(module_name); }
+	const ModuleTiming& at(RTLIL::IdString module_name) const { return data.at(module_name); }
 };
 
 YOSYS_NAMESPACE_END
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8337b61b1..f7097fadb 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -266,8 +266,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	for (auto &it : bit_users)
 		if (bit_drivers.count(it.first))
 			for (auto driver_cell : bit_drivers.at(it.first))
-			for (auto user_cell : it.second)
-				toposort.edge(driver_cell, user_cell);
+				for (auto user_cell : it.second)
+					toposort.edge(driver_cell, user_cell);
 
 	if (ys_debug(1))
 		toposort.analyze_loops = true;
@@ -382,7 +382,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 
 void prep_delays(RTLIL::Design *design, bool dff_mode)
 {
-        TimingInfo timing;
+	TimingInfo timing;
 
 	// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
 	//   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
@@ -412,7 +412,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 			if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
 				flops.insert(inst_module);
 				continue; // do not add $__ABC9_DELAY boxes to flops
-					  //   as delays will be captured in the flop box
+				//   as delays will be captured in the flop box
 			}
 
 			if (!timing.count(derived_type))
@@ -463,7 +463,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 
 void prep_lut(RTLIL::Design *design, int maxlut)
 {
-        TimingInfo timing;
+	TimingInfo timing;
 
 	std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
 	for (auto module : design->modules()) {
@@ -482,7 +482,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 			else if (o != d)
 				log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
 			specify.push_back(i.second);
-                }
+		}
 
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
@@ -523,7 +523,7 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
 
 void prep_box(RTLIL::Design *design, bool dff_mode)
 {
-        TimingInfo timing;
+	TimingInfo timing;
 
 	std::stringstream ss;
 	int abc9_box_id = 1;
@@ -581,21 +581,21 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 						first = false;
 					else
 						ss << " ";
-                                        auto it = t.find(wire);
-                                        if (it == t.end())
+					auto it = t.find(wire);
+					if (it == t.end())
 						// Assume that no setup time means zero
-                                                ss << 0;
-                                        else {
-                                                ss << it->second;
+						ss << 0;
+					else {
+						ss << it->second;
 
 #ifndef NDEBUG
-                                                if (ys_debug(1)) {
-                                                        static std::set<std::pair<IdString,IdString>> seen;
-                                                        if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
-                                                                        log_id(port_name), it->second);
-                                                }
+						if (ys_debug(1)) {
+							static std::set<std::pair<IdString,IdString>> seen;
+							if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
+									log_id(port_name), it->second);
+						}
 #endif
-                                        }
+					}
 
 				}
 				// Last input is 'abc9_ff.Q'

From 9dcf204dece518a48192a90ea962a9d630283e11 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 08:41:48 -0800
Subject: [PATCH 36/46] TimingInfo: index by (port_name,offset)

---
 kernel/timinginfo.h        | 28 +++++++++++++++++++---------
 passes/techmap/abc9_ops.cc |  7 ++++---
 2 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index e2af4d51a..8d0904175 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -25,17 +25,27 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-typedef std::pair<RTLIL::SigBit,RTLIL::SigBit> BitBit;
-
-struct ModuleTiming
-{
-	RTLIL::IdString type;
-	dict<BitBit, int> comb;
-	dict<RTLIL::SigBit, int> arrival, required;
-};
-
 struct TimingInfo
 {
+	struct NameBit
+	{
+		RTLIL::IdString name;
+		int offset;
+		NameBit() {}
+		NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
+		bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
+		bool operator!=(const NameBit& nb) const { return !operator==(nb); }
+		unsigned int hash() const { return mkhash_add(name.hash(), offset); }
+	};
+	typedef std::pair<NameBit,NameBit> BitBit;
+
+	struct ModuleTiming
+	{
+		RTLIL::IdString type;
+		dict<BitBit, int> comb;
+		dict<NameBit, int> arrival, required;
+	};
+
 	dict<RTLIL::IdString, ModuleTiming> data;
 
 	TimingInfo()
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index f7097fadb..e5de2bcc4 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -473,11 +473,11 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 
 		auto &t = timing.setup_module(module);
 
-		SigBit o;
+		TimingInfo::NameBit o;
 		std::vector<int> specify;
 		for (const auto &i : t.comb) {
 			auto &d = i.first.second;
-			if (o == SigBit())
+			if (o == TimingInfo::NameBit())
 				o = d;
 			else if (o != d)
 				log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
@@ -581,7 +581,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 						first = false;
 					else
 						ss << " ";
-					auto it = t.find(wire);
+					log_assert(GetSize(wire) == 1);
+					auto it = t.find(SigBit(wire,0));
 					if (it == t.end())
 						// Assume that no setup time means zero
 						ss << 0;

From 6bb3d9f9c09993960a5a91fa51f163a7e67e2503 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 11:02:28 -0800
Subject: [PATCH 37/46] Make TimingInfo::TimingInfo(SigBit) constructor
 explicit

---
 backends/aiger/xaiger.cc   | 2 +-
 kernel/timinginfo.h        | 9 +++++----
 passes/techmap/abc9_ops.cc | 6 +++---
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index dc0f997fe..402f41597 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -263,7 +263,7 @@ struct XAigerWriter
 						continue;
 
 					for (int i = 0; i < GetSize(conn.second); i++) {
-						auto d = t.at(SigBit(port_wire,i), 0);
+						auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
 						if (d == 0)
 							continue;
 
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 8d0904175..7855ddd15 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -31,8 +31,9 @@ struct TimingInfo
 	{
 		RTLIL::IdString name;
 		int offset;
-		NameBit() {}
-		NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
+		NameBit() : offset(0) {}
+		NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
+		explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
 		bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
 		bool operator!=(const NameBit& nb) const { return !operator==(nb); }
 		unsigned int hash() const { return mkhash_add(name.hash(), offset); }
@@ -127,7 +128,7 @@ struct TimingInfo
 					continue;
 				}
 				for (const auto &d : dst) {
-					auto &v = t.arrival[d];
+					auto &v = t.arrival[NameBit(d)];
 					v = std::max(v, max);
 				}
 			}
@@ -151,7 +152,7 @@ struct TimingInfo
 					continue;
 				}
 				for (const auto &s : src) {
-					auto &v = t.required[s];
+					auto &v = t.required[NameBit(s)];
 					v = std::max(v, max);
 				}
 			}
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index e5de2bcc4..e46ad0a02 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -440,7 +440,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
 
 			SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
 			for (int i = 0; i < GetSize(conn.second); i++) {
-				auto d = t.at(SigBit(port_wire,i), 0);
+				auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
 				if (d == 0)
 					continue;
 
@@ -582,7 +582,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 					else
 						ss << " ";
 					log_assert(GetSize(wire) == 1);
-					auto it = t.find(SigBit(wire,0));
+					auto it = t.find(TimingInfo::NameBit(port_name,0));
 					if (it == t.end())
 						// Assume that no setup time means zero
 						ss << 0;
@@ -680,7 +680,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 					first = false;
 				else
 					ss << " ";
-				auto jt = t.find(std::make_pair(i,o));
+				auto jt = t.find(std::make_pair(TimingInfo::NameBit(i),TimingInfo::NameBit(o)));
 				if (jt == t.end())
 					ss << "-";
 				else

From 3b74e0fa45a93f23448215ef9148ddc7bcd78cd7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 11:03:38 -0800
Subject: [PATCH 38/46] xilinx: add delays to INV

---
 techlibs/xilinx/cells_sim.v | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 0896f3176..df3b554c1 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -160,6 +160,9 @@ module INV(
     input I
 );
   assign O = !I;
+  specify
+    (I => O) = 127;
+  endspecify
 endmodule
 
 (* abc9_lut=1 *)

From 6bd95501005523604d4828d1635c49e439472f79 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 11:03:59 -0800
Subject: [PATCH 39/46] ice40: add delays to SB_CARRY

---
 techlibs/ice40/cells_sim.v | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index f9f8c9e66..84b07b934 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -211,6 +211,36 @@ endmodule
 (* lib_whitebox *)
 module SB_CARRY (output CO, input I0, I1, CI);
 	assign CO = (I0 && I1) || ((I0 || I1) && CI);
+`ifdef ICE40_HX
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L79
+		(CI => CO) = (126, 105);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L82
+		(I0 => CO) = (259, 245);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_hx1k.txt#L85
+		(I1 => CO) = (231, 133);
+	endspecify
+`endif
+`ifdef ICE40_LP
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L79
+		(CI => CO) = (186, 155);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L82
+		(I0 => CO) = (382, 362);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_lp1k.txt#L85
+		(I0 => CO) = (341, 196);
+	endspecify
+`endif
+`ifdef ICE40_U
+	specify
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L91
+		(CI => CO) = (278, 278);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L94
+		(I0 => CO) = (675, 662);
+		// https://github.com/cliffordwolf/icestorm/blob/be0bca0230d6fe1102e0a360b953fbb0d273a39f/icefuzz/timings_up5k.txt#L97
+		(I0 => CO) = (609, 358);
+	endspecify
+`endif
 endmodule
 
 // Positive Edge SiliconBlue FF Cells

From 376319dc8d96b7592cda5c0249228dd6a26ea5a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 14:28:52 -0800
Subject: [PATCH 40/46] xilinx: Update RAMB* specify entries

---
 techlibs/xilinx/cells_sim.v | 53 +++++++++++++++++++++++++++++--------
 1 file changed, 42 insertions(+), 11 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index df3b554c1..ed7ac2026 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -3740,6 +3740,14 @@ module RAMB18E1 (
         $setup(WEA, posedge CLKARDCLK, 532);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
         $setup(WEBWE, posedge CLKBWRCLK, 532);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29
+        $setup(REGCEAREGCE, posedge CLKARDCLK, 360);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31
+        $setup(RSTREGARSTREG, posedge CLKARDCLK, 342);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49
+        $setup(REGCEB, posedge CLKBWRCLK, 360);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59
+        $setup(RSTREGB, posedge CLKBWRCLK, 342);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
         $setup(DIADI, posedge CLKARDCLK, 737);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
@@ -3749,13 +3757,21 @@ module RAMB18E1 (
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
         $setup(DIPBDIP, posedge CLKBWRCLK, 737);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
-        (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454;
-        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
-        (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454;
+        if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 2454;
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
-        (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454;
+        if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153
+        if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 16'bx)) = 882;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154
+        if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 2'bx)) = 882;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
+        if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 2454;
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
-        (posedge CLKARDCLK => (DOPBDOP : 2'bx)) = 2454;
+        if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173
+        if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 16'bx)) = 882;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174
+        if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 2'bx)) = 882;
     endspecify
 endmodule
 
@@ -3988,6 +4004,14 @@ module RAMB36E1 (
         $setup(WEA, posedge CLKARDCLK, 532);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L21
         $setup(WEBWE, posedge CLKBWRCLK, 532);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L29
+        $setup(REGCEAREGCE, posedge CLKARDCLK, 360);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L31
+        $setup(RSTREGARSTREG, posedge CLKARDCLK, 342);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L49
+        $setup(REGCEB, posedge CLKBWRCLK, 360);
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L59
+        $setup(RSTREGB, posedge CLKBWRCLK, 342);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L123
         $setup(DIADI, posedge CLKARDCLK, 737);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L133
@@ -3997,14 +4021,21 @@ module RAMB36E1 (
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L135
         $setup(DIPBDIP, posedge CLKBWRCLK, 737);
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L143
-        (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454;
-        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
-        (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454;
+        if (&DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 2454;
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L144
-        (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454;
+        if (&DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L153
+        if (|DOA_REG) (posedge CLKARDCLK => (DOADO : 32'bx)) = 882;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L154
+        if (|DOA_REG) (posedge CLKARDCLK => (DOPADOP : 4'bx)) = 882;
+        // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L163
+        if (&DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 2454;
         // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/BRAM_L.sdf#L164
-        (posedge CLKARDCLK => (DOPBDOP : 4'bx)) = 2454;
+        if (&DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 2454;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L173
+        if (|DOB_REG) (posedge CLKBWRCLK => (DOBDO : 32'bx)) = 882;
+        // https://github.com/SymbiFlow/prjxray-db/blob/4bc6385ab300b1819848371f508185f57b649a0e/artix7/timings/BRAM_L.sdf#L174
+        if (|DOB_REG) (posedge CLKBWRCLK => (DOPBDOP : 4'bx)) = 882;
     endspecify
 endmodule
 
-

From 88d5997c80e5c2bebb479f76b123899c6de48c57 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 14:31:24 -0800
Subject: [PATCH 41/46] abc9_ops: suppress -prep_box warning for abc9_flop

---
 passes/techmap/abc9_ops.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index e46ad0a02..cffcc189e 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -670,7 +670,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 		ss << std::endl;
 
 		auto &t = timing.setup_module(module).comb;
-		if (t.empty())
+		if (!abc9_flop && t.empty())
 			log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
 
 		for (const auto &o : outputs) {

From e79376d6cb34d5c569a95ba0717be214aeac0556 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 18 Feb 2020 15:32:56 -0800
Subject: [PATCH 42/46] ast: quiet down when deriving blackbox modules

---
 frontends/ast/ast.cc | 30 +++++++++++++++++++-----------
 frontends/ast/ast.h  |  2 +-
 2 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 239813810..3254012bd 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -939,14 +939,15 @@ RTLIL::Const AstNode::realAsConst(int width)
 }
 
 // create a new AstModule from an AST_MODULE AST node
-static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL)
+static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL, bool quiet = false)
 {
 	log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
 
 	if (defer)
 		log("Storing AST representation for module `%s'.\n", ast->str.c_str());
-	else
+	else if (!quiet) {
 		log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
+	}
 
 	current_module = new AstModule;
 	current_module->ast = NULL;
@@ -1484,14 +1485,16 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
 RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool /*mayfail*/)
 {
+	bool quiet = lib || attributes.count(ID(blackbox)) || attributes.count(ID(whitebox));
+
 	AstNode *new_ast = NULL;
-	std::string modname = derive_common(design, parameters, &new_ast);
+	std::string modname = derive_common(design, parameters, &new_ast, quiet);
 
 	if (!design->has(modname)) {
 		new_ast->str = modname;
-		design->add(process_module(new_ast, false));
+		design->add(process_module(new_ast, false, NULL, quiet));
 		design->module(modname)->check();
-	} else {
+	} else if (!quiet) {
 		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
 	}
 
@@ -1500,7 +1503,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 }
 
 // create a new parametric module (when needed) and return the name of the generated module
-std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out)
+std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet)
 {
 	std::string stripped_name = name.str();
 
@@ -1516,13 +1519,15 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
 		para_counter++;
 		std::string para_id = child->str;
 		if (parameters.count(para_id) > 0) {
-			log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
+			if (!quiet)
+				log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
 			para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
 			continue;
 		}
 		para_id = stringf("$%d", para_counter);
 		if (parameters.count(para_id) > 0) {
-			log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
+			if (!quiet)
+				log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
 			para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
 			continue;
 		}
@@ -1539,7 +1544,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
 	if (design->has(modname))
 		return modname;
 
-	log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
+	if (!quiet)
+		log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
 	loadconfig();
 
 	AstNode *new_ast = ast->clone();
@@ -1550,12 +1556,14 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
 		para_counter++;
 		std::string para_id = child->str;
 		if (parameters.count(para_id) > 0) {
-			log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
+			if (!quiet)
+				log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
 			goto rewrite_parameter;
 		}
 		para_id = stringf("$%d", para_counter);
 		if (parameters.count(para_id) > 0) {
-			log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
+			if (!quiet)
+				log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
 			goto rewrite_parameter;
 		}
 		continue;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index a50ae306d..59e6058a7 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -307,7 +307,7 @@ namespace AST
 		~AstModule() YS_OVERRIDE;
 		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
 		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;
-		std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out);
+		std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool quiet = false);
 		void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
 		RTLIL::Module *clone() const YS_OVERRIDE;
 		void loadconfig() const;

From a179d918ec4e5ed595e8f556b159ab39679d4e6c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 19 Feb 2020 09:47:36 -0800
Subject: [PATCH 43/46] Revert "Fix tests/arch/xilinx/fsm.ys to count flops
 only"

This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
---
 tests/arch/xilinx/fsm.ys | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index 70c05f2c0..fec4c6082 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -15,7 +15,10 @@ stat
 select -assert-count 1 t:BUFG
 select -assert-count 4 t:FDRE
 select -assert-count 1 t:FDSE
-select -assert-none t:BUFG t:FDRE t:FDSE t:LUT* %% t:* %D
+select -assert-count 1 t:LUT2
+select -assert-count 3 t:LUT5
+select -assert-count 1 t:LUT6
+select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
 
 design -load orig
 
@@ -28,5 +31,8 @@ cd fsm # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 6 t:FDRE
-# FIXME: One more register than above?
-select -assert-none t:BUFG t:FDRE t:LUT* t:MUXF* %% t:* %D
+select -assert-count 1 t:LUT1
+select -assert-count 3 t:LUT3
+select -assert-count 6 t:LUT4
+select -assert-count 6 t:MUXF5
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:LUT4 t:MUXF5 %% t:* %D

From 78929e8c3d399d47a36bb974eed74e53a3840402 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Feb 2020 07:52:08 -0800
Subject: [PATCH 44/46] Fixes for older compilers

---
 kernel/timinginfo.h        | 9 ++++++++-
 passes/techmap/abc9_ops.cc | 2 +-
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 7855ddd15..5a6f4aa28 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -38,7 +38,14 @@ struct TimingInfo
 		bool operator!=(const NameBit& nb) const { return !operator==(nb); }
 		unsigned int hash() const { return mkhash_add(name.hash(), offset); }
 	};
-	typedef std::pair<NameBit,NameBit> BitBit;
+	struct BitBit
+	{
+		NameBit first, second;
+		BitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}
+		BitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}
+		bool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }
+		unsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }
+	};
 
 	struct ModuleTiming
 	{
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index cffcc189e..b0bd81698 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -680,7 +680,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
 					first = false;
 				else
 					ss << " ";
-				auto jt = t.find(std::make_pair(TimingInfo::NameBit(i),TimingInfo::NameBit(o)));
+				auto jt = t.find(TimingInfo::BitBit(i,o));
 				if (jt == t.end())
 					ss << "-";
 				else

From 0f4c1906bb82f03f77683b71e597ed4802fe316a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Feb 2020 10:29:53 -0800
Subject: [PATCH 45/46] Small fixes

---
 README.md           | 12 ++++++------
 kernel/timinginfo.h |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/README.md b/README.md
index 08d4cb0d7..79801d23f 100644
--- a/README.md
+++ b/README.md
@@ -364,13 +364,13 @@ Verilog Attributes and non-standard features
   it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
   from inserting another pad cell on it.
 
-- The module attribute ``abc9_lut`` is an integer attribute marking to `abc9`
-  that this module describes a LUT with propagation delays described using
-  `specify` statements.
+- The module attribute ``abc9_lut`` is an integer attribute indicating to
+  `abc9` that this module describes a LUT with an area cost of this value, and
+  propagation delays described using `specify` statements.
 
-- The module attribute ``abc9_box`` is a boolean specifying a blackbox or
-  whitebox definition, with propagation delays described using `specify`
-  statements, for use by `abc9`.
+- The module attribute ``abc9_box`` is a boolean specifying a black/white-box
+  definition, with propagation delays described using `specify` statements, for
+  use by `abc9`.
 
 - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and
   carry-out (if output port) ports of a box. This information is necessary for
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 5a6f4aa28..4b77c02e8 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -18,8 +18,8 @@
  *
  */
 
-#ifndef TIMINGARCS_H
-#define TIMINGARCS_H
+#ifndef TIMINGINFO_H
+#define TIMINGINFO_H
 
 #include "kernel/yosys.h"
 

From 090e54569a58b26d616806337c28507d199ca43c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 27 Feb 2020 10:33:04 -0800
Subject: [PATCH 46/46] Remove RAMB{18,36}E1 from cells_xtra.py

---
 techlibs/xilinx/cells_xtra.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py
index ca301685b..749b1e0a7 100644
--- a/techlibs/xilinx/cells_xtra.py
+++ b/techlibs/xilinx/cells_xtra.py
@@ -163,8 +163,8 @@ CELLS = [
     # Virtex 6 / Series 7.
     Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
-    Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
-    Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
+    #Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
+    #Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']]}),
     # Ultrascale.
     Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),
     Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}),