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Tests: Add testcase for problematic ABC DONE check

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Krystine Sherwin 2025-11-21 14:46:01 +13:00
parent 8ea51e1479
commit 4d1b688717
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tests/techmap/bug5495.v Normal file
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module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule