From 4d1b68871746e469a71eaeab3036a71ca04bdc00 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 21 Nov 2025 14:46:01 +1300
Subject: [PATCH] Tests: Add testcase for problematic ABC DONE check

---
 tests/techmap/bug5495.abc | 2 ++
 tests/techmap/bug5495.sh  | 7 +++++++
 tests/techmap/bug5495.v   | 7 +++++++
 3 files changed, 16 insertions(+)
 create mode 100644 tests/techmap/bug5495.abc
 create mode 100755 tests/techmap/bug5495.sh
 create mode 100644 tests/techmap/bug5495.v

diff --git a/tests/techmap/bug5495.abc b/tests/techmap/bug5495.abc
new file mode 100644
index 000000000..60a29a58a
--- /dev/null
+++ b/tests/techmap/bug5495.abc
@@ -0,0 +1,2 @@
+
+fraig_store; fraig_restore
diff --git a/tests/techmap/bug5495.sh b/tests/techmap/bug5495.sh
new file mode 100755
index 000000000..181797e32
--- /dev/null
+++ b/tests/techmap/bug5495.sh
@@ -0,0 +1,7 @@
+#!/usr/bin/env bash
+
+if ! timeout 5 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then
+    echo "Yosys failed to complete"
+    exit 1
+fi
+
diff --git a/tests/techmap/bug5495.v b/tests/techmap/bug5495.v
new file mode 100644
index 000000000..37ce73ec8
--- /dev/null
+++ b/tests/techmap/bug5495.v
@@ -0,0 +1,7 @@
+module simple(I1, I2, O);
+	input wire I1;
+	input wire I2;
+	output wire O;
+
+	assign O = I1 | I2;
+endmodule