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Add simple VHDL+PSL example

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This commit is contained in:
Clifford Wolf 2017-07-28 15:33:30 +02:00
parent 5a828fff34
commit 4cf890dac1
4 changed files with 64 additions and 17 deletions
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2
tests/sva/.gitignore vendored
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@ -3,3 +3,5 @@
/*_pass
/*_fail
/*.ok
/vhdlpsl[0-9][0-9]
/vhdlpsl[0-9][0-9].sby