Merge pull request #5095 from YosysHQ/emil/one-bit-width

rtlil: enable single-bit vector wires

backends/verilog/verilog_backend.cc

@@ -383,6 +383,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 	if (attr2comment)
 		as_comment = true;
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
+		if (it->first == ID::single_bit_vector) continue;
 		if (it->first == ID::init && regattr) continue;
 		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
@@ -419,6 +420,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 			range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset);
 		else
 			range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset);
+	} else {
+		if (wire->attributes.count(ID::single_bit_vector))
+			range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
 	}
 	if (wire->port_input && !wire->port_output)
 		f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());

frontends/ast/genrtlil.cc

@@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			wire->port_input = is_input;
 			wire->port_output = is_output;
 			wire->upto = range_swapped;
+
 			wire->is_signed = is_signed;
 
 			for (auto &attr : attributes) {

frontends/ast/simplify.cc

@@ -2086,6 +2086,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 					std::swap(range_left, range_right);
 					range_swapped = force_upto;
 				}
+				if (range_left == range_right)
+					set_attribute(ID::single_bit_vector, mkconst_int(1, false));
 			}
 		} else {
 			if (!range_valid)
@@ -2094,6 +2096,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 			range_swapped = false;
 			range_left = 0;
 			range_right = 0;
+			if (attributes.count(ID::single_bit_vector)) {
+				delete attributes[ID::single_bit_vector];
+				attributes.erase(ID::single_bit_vector);
+			}
 		}
 	}
 

frontends/verific/verific.cc

@@ -1557,6 +1557,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
 		wire->upto = portbus->IsUp();
 		import_attributes(wire->attributes, portbus, nl, portbus->Size());
+		if (portbus->Size() == 1)
+			wire->set_bool_attribute(ID::single_bit_vector);
 		SetIter si ;
 		Port *port ;
 		FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
@@ -1755,6 +1757,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				break;
 			}
 			import_attributes(wire->attributes, netbus, nl, netbus->Size());
+			if (netbus->Size() == 1)
+				wire->set_bool_attribute(ID::single_bit_vector);
 
 			RTLIL::Const initval = Const(State::Sx, GetSize(wire));
 			bool initval_valid = false;

kernel/constids.inc

@@ -184,6 +184,7 @@ X(romstyle)
 X(S)
 X(SET)
 X(SET_POLARITY)
+X(single_bit_vector)
 X(SIZE)
 X(SRC)
 X(src)

tests/verilog/sbvector.ys

@@ -0,0 +1,30 @@
+read_verilog <<EOT
+module foo(
+	output o,
+	input [0:0] i1,
+	input i2
+);
+    wire [0:0] w1 = i1 ^ i2;
+    wire w2 = ~i1;
+	assign o = w1 ^ w2;
+endmodule
+EOT
+
+hierarchy
+proc
+select -assert-count 1 w:i1
+select -assert-count 1 w:i1 a:single_bit_vector %i
+select -assert-count 1 w:i2
+select -assert-count 0 w:i2 a:single_bit_vector %i
+select -assert-count 1 w:w1
+select -assert-count 1 w:w1 a:single_bit_vector %i
+select -assert-count 1 w:w2
+select -assert-count 0 w:w2 a:single_bit_vector %i
+
+write_verilog verilog_sbvector.out
+!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
+!grep -qF 'input [0:0] i1;' verilog_sbvector.out
+!grep -qF 'wire i2;' verilog_sbvector.out
+!grep -qF 'input i2;' verilog_sbvector.out
+!grep -qF 'wire [0:0] w1;' verilog_sbvector.out
+!grep -qF 'wire w2;' verilog_sbvector.out