From 5e72464a15b70b25d89bd2cd999c76e7d8506b32 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 6 May 2025 12:02:00 +0200 Subject: [PATCH 1/3] rtlil: enable single-bit vector wires --- backends/verilog/verilog_backend.cc | 3 +++ frontends/ast/genrtlil.cc | 1 + frontends/ast/simplify.cc | 6 ++++++ kernel/constids.inc | 1 + tests/verilog/sbvector.ys | 20 ++++++++++++++++++++ 5 files changed, 31 insertions(+) create mode 100644 tests/verilog/sbvector.ys diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 2bc6ff3b8..1b828dcbd 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -419,6 +419,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire) range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset); else range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset); + } else { + if (wire->attributes.count(ID::single_bit_vector)) + range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset); } if (wire->port_input && !wire->port_output) f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d3982b92b..26ed0e3e4 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->port_input = is_input; wire->port_output = is_output; wire->upto = range_swapped; + wire->is_signed = is_signed; for (auto &attr : attributes) { diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 3411d6c03..a45eb1cc1 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2084,6 +2084,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin std::swap(range_left, range_right); range_swapped = force_upto; } + if (range_left == range_right) + set_attribute(ID::single_bit_vector, mkconst_int(1, false)); } } else { if (!range_valid) @@ -2092,6 +2094,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin range_swapped = false; range_left = 0; range_right = 0; + if (attributes.count(ID::single_bit_vector)) { + delete attributes[ID::single_bit_vector]; + attributes.erase(ID::single_bit_vector); + } } } diff --git a/kernel/constids.inc b/kernel/constids.inc index 4fdbb3dc8..055ebf2a8 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -184,6 +184,7 @@ X(romstyle) X(S) X(SET) X(SET_POLARITY) +X(single_bit_vector) X(SIZE) X(SRC) X(src) diff --git a/tests/verilog/sbvector.ys b/tests/verilog/sbvector.ys new file mode 100644 index 000000000..3481f6f45 --- /dev/null +++ b/tests/verilog/sbvector.ys @@ -0,0 +1,20 @@ +read_verilog < Date: Mon, 12 May 2025 13:23:02 +0200 Subject: [PATCH 2/3] verific: support single_bit_vector --- frontends/verific/verific.cc | 4 ++++ tests/verilog/sbvector.ys | 20 +++++++++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 95bede420..411804566 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1557,6 +1557,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl, portbus->Size()); + if (portbus->Size() == 1) + wire->set_bool_attribute(ID::single_bit_vector); SetIter si ; Port *port ; FOREACH_PORT_OF_PORTBUS(portbus, si, port) { @@ -1755,6 +1757,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma break; } import_attributes(wire->attributes, netbus, nl, netbus->Size()); + if (netbus->Size() == 1) + wire->set_bool_attribute(ID::single_bit_vector); RTLIL::Const initval = Const(State::Sx, GetSize(wire)); bool initval_valid = false; diff --git a/tests/verilog/sbvector.ys b/tests/verilog/sbvector.ys index 3481f6f45..ab8092700 100644 --- a/tests/verilog/sbvector.ys +++ b/tests/verilog/sbvector.ys @@ -4,17 +4,27 @@ module foo( input [0:0] i1, input i2 ); - assign o = i1 ^ i2; + wire [0:0] w1 = i1 ^ i2; + wire w2 = ~i1; + assign o = w1 ^ w2; endmodule EOT -logger -expect log "wire width 1 input 2 \\i1" 1 -logger -expect log "wire input 3 \\i2" 1 -dump -logger -check-expected +hierarchy +proc +select -assert-count 1 w:i1 +select -assert-count 1 w:i1 a:single_bit_vector %i +select -assert-count 1 w:i2 +select -assert-count 0 w:i2 a:single_bit_vector %i +select -assert-count 1 w:w1 +select -assert-count 1 w:w1 a:single_bit_vector %i +select -assert-count 1 w:w2 +select -assert-count 0 w:w2 a:single_bit_vector %i write_verilog verilog_sbvector.out !grep -qF 'wire [0:0] i1;' verilog_sbvector.out !grep -qF 'input [0:0] i1;' verilog_sbvector.out !grep -qF 'wire i2;' verilog_sbvector.out !grep -qF 'input i2;' verilog_sbvector.out +!grep -qF 'wire [0:0] w1;' verilog_sbvector.out +!grep -qF 'wire w2;' verilog_sbvector.out From f73c6a9c9ac1dcaee9ce283c73a6cf9fae07bc6e Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 12 May 2025 13:36:25 +0200 Subject: [PATCH 3/3] write_verilog: don't dump single_bit_vector attribute --- backends/verilog/verilog_backend.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 1b828dcbd..10cf7c52e 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -383,6 +383,7 @@ void dump_attributes(std::ostream &f, std::string indent, dictfirst == ID::single_bit_vector) continue; if (it->first == ID::init && regattr) continue; f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = ");