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https://github.com/YosysHQ/yosys
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Merge 6d62199805 into 09f9e0e8d1
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nataliakokoromyti
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3 changed files with 291 additions and 0 deletions
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@ -7,6 +7,7 @@ OBJS += passes/techmap/booth.o
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OBJS += passes/techmap/libparse.o
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OBJS += passes/techmap/libcache.o
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OBJS += passes/techmap/breaksop.o
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ifeq ($(ENABLE_ABC),1)
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OBJS += passes/techmap/abc.o
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OBJS += passes/techmap/abc9.o
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96
passes/techmap/breaksop.cc
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96
passes/techmap/breaksop.cc
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@ -0,0 +1,96 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Robert Ou <rqou@robertou.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct BreakSopPass : public Pass {
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BreakSopPass() : Pass("breaksop", "break $sop cells into $reduce_and/$reduce_or cells") { }
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void help() override
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{
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log("\n");
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log(" breaksop [selection]\n");
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log("\n");
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log("Break $sop cells into $reduce_and/$reduce_or cells.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing BREAKSOP pass (break $sop cells into $reduce_and/$reduce_or cells).\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules())
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{
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// Data structures
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pool<Cell*> cells_to_remove;
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SigMap sigmap(module);
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// Process $sop cells
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for (auto cell : module->selected_cells())
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{
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if (cell->type == ID($sop))
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{
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// Read the inputs/outputs/parameters of the $sop cell
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auto sop_inputs = sigmap(cell->getPort(ID::A));
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auto sop_output = sigmap(cell->getPort(ID::Y))[0];
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auto sop_depth = cell->getParam(ID::DEPTH).as_int();
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auto sop_width = cell->getParam(ID::WIDTH).as_int();
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auto sop_table = cell->getParam(ID::TABLE);
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// Get $sop output wire name
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module->rename(cell->name, module->uniquify(sop_output.wire->name.str() + "_sop"));
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// Construct $reduce_and cells
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pool<SigBit> intermed_wires;
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for (int i = 0; i < sop_depth; i++) {
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// Wire for the output
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auto and_out = module->addWire(NEW_ID_SUFFIX("andterm_out"));
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intermed_wires.insert(and_out);
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// Signals for the inputs
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pool<SigBit> and_in;
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for (int j = 0; j < sop_width; j++)
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if (sop_table[2 * (i * sop_width + j) + 0])
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and_in.insert(module->Not(NEW_ID_SUFFIX(stringf("sop_in_%d_comp", j)), sop_inputs[j], false, cell->get_src_attribute()));
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else if (sop_table[2 * (i * sop_width + j) + 1])
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and_in.insert(sop_inputs[j]);
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// Construct the cell
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module->addReduceAnd(NEW_ID_SUFFIX("andterm"), and_in, and_out, false, cell->get_src_attribute());
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}
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// Construct the $reduce_or cell
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module->addReduceOr(NEW_ID_SUFFIX("orterm"), intermed_wires, sop_output, false, cell->get_src_attribute());
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// Mark the $sop cell for removal
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cells_to_remove.insert(cell);
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}
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}
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// Perform removal of $sop cells
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for (auto cell : cells_to_remove)
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module->remove(cell);
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}
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}
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} BreakSopPass;
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PRIVATE_NAMESPACE_END
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194
tests/techmap/breaksop.ys
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194
tests/techmap/breaksop.ys
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@ -0,0 +1,194 @@
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log -header "Simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] a,
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output wire x
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);
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assign x = a[0] | (a[1] & a[2]);
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endmodule
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EOF
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check -assert
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# Generate $sop
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techmap
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abc -sop
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select -assert-count 1 t:$sop
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# Check equivalence after breaksop
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$reduce_and
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select -assert-count 1 t:$reduce_or
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design -reset
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log -pop
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log -header "With negation"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [2:0] a,
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output wire x
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);
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assign x = ~a[0] | (~a[1] & ~a[2]);
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endmodule
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EOF
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check -assert
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# Generate $sop
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techmap
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abc -sop
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select -assert-count 1 t:$sop
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# Check equivalence after breaksop
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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write_verilog dump_post.v
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select -assert-count 2 t:$reduce_and
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select -assert-count 1 t:$reduce_or
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design -reset
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log -pop
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log -header "More depth"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = (a[0] & a[1]) | (~a[2] & a[3]) | (a[0] & ~a[1] & a[2]);
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endmodule
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EOF
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check -assert
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# Generate $sop
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techmap
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abc -sop
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select -assert-count 1 t:$sop
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# Check equivalence after breaksop
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$reduce_and
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select -assert-count 1 t:$reduce_or
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design -reset
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log -pop
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log -header "Only ORs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = a[0] | a[1] | a[2] | a[3];
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endmodule
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EOF
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check -assert
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# Generate $sop
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techmap
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abc -sop
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select -assert-count 1 t:$sop
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# Check equivalence after breaksop
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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# We only have one AND gate since breaksop turns the OR gate into an AND gate
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# The inputs to this gate are inverted and the outputs are also inverted, so with
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# DeMorgan's law, they are equivalent
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design -load postopt
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opt # Run opt to remove unneeded OR gate
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select -assert-count 1 t:$reduce_and
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select -assert-count 0 t:$reduce_or
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design -reset
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log -pop
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log -header "With constants"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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output wire x
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);
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assign x = (~a[0] & 1'b1) | (a[1] & 1'b0) | (a[2] & a[3]);
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endmodule
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EOF
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check -assert
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# Generate $sop
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techmap
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abc -sop
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select -assert-count 1 t:$sop
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# Check equivalence after breaksop
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write_verilog dump_pre.v
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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opt
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write_verilog dump_post.v
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select -assert-count 2 t:$reduce_and
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select -assert-count 1 t:$reduce_or
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design -reset
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log -pop
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log -header "Multiple sops"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [3:0] a,
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input wire [3:0] b,
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output wire x,
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output wire y
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);
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assign x = (a[0] & a[1]) | (~a[2] & a[3]) | (a[0] & ~a[1] & a[2]);
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assign y = (b[0] & b[1]) | (~b[2] & b[3]) | (b[0] & ~b[1] & b[2]);
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endmodule
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EOF
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check -assert
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# Generate $sop
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techmap
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abc -sop
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select -assert-count 2 t:$sop
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# Check equivalence after breaksop
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equiv_opt -assert breaksop
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 6 t:$reduce_and
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select -assert-count 2 t:$reduce_or
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design -reset
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log -pop
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