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analogdevices: (some) Native BRAM

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Specifically, the SDP configurations for RBRAM (ignoring 2048x09 because it makes the memlib format unhappy).
Drop the unused defines from the synth pass.
Remove comments from the lutram files referencing xilinx.
This commit is contained in:
Krystine Sherwin 2025-10-08 17:32:46 +13:00
parent e8127ff5f3
commit 4a99aa09cb
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6 changed files with 116 additions and 875 deletions
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192
techlibs/analogdevices/brams.txt
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@ -1,165 +1,39 @@
# Block RAMs for Virtex 4+.
# The corresponding mapping files are:
# - brams_xc6v_map.v: Virtex 6, Series 7
# Simple Dual Port
# Supported:
# SDP_4096x05
# SDP_2048x10
# SDP_1024x40
# Ignored:
# SDP_2048x09
ram block $__ANALOGDEVICES_BLOCKRAM_TDP_ {
byte 9;
ifdef HAS_SIZE_36 {
option "MODE" "HALF" {
abits 14;
widths 1 2 4 9 18 per_port;
cost 129;
}
option "MODE" "FULL" {
abits 15;
widths 1 2 4 9 18 36 per_port;
cost 257;
}
ifdef HAS_CASCADE {
option "MODE" "CASCADE" {
abits 16;
# hack to enforce same INIT layout as in the other modes
widths 1 2 4 9 per_port;
cost 513;
}
}
} else {
option "MODE" "FULL" {
abits 14;
widths 1 2 4 9 18 36 per_port;
cost 129;
}
ifdef HAS_CASCADE {
option "MODE" "CASCADE" {
abits 15;
widths 1 2 4 9 per_port;
cost 257;
}
}
ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
option "ENABLE_WIDTH" "BIT" {
abits 12;
widths 5 10 global;
byte 1;
cost 1;
}
init any;
port srsw "A" "B" {
option "MODE" "HALF" {
width mix;
}
option "MODE" "FULL" {
width mix;
}
option "MODE" "CASCADE" {
width mix 1;
}
ifdef HAS_ADDRCE {
# TODO
# addrce;
}
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
ifdef HAS_CONFLICT_BUG {
option "HAS_RDFIRST" 1 {
clock posedge "C";
}
option "HAS_RDFIRST" 0 {
clock posedge;
}
} else {
clock posedge;
}
option "ENABLE_WIDTH" "BYTE" {
abits 10;
width 40;
byte 8;
cost 4;
}
# Unclear if/how RBRAM is initialized, default SIM_INIT_BEHAVIOUR is UNINITIALIZED
init none;
port sr "R" {
clock anyedge;
clken;
}
port sw "W" {
clock anyedge;
clken;
rdsrst any gated_clken;
rdinit any;
portoption "WRITE_MODE" "NO_CHANGE" {
rdwr no_change;
option "MODE" "CASCADE" {
forbid;
}
}
portoption "WRITE_MODE" "WRITE_FIRST" {
ifdef HAS_SIZE_36 {
rdwr new;
} else {
rdwr new_only;
}
}
ifdef HAS_CONFLICT_BUG {
option "HAS_RDFIRST" 1 {
portoption "WRITE_MODE" "READ_FIRST" {
rdwr old;
wrtrans all old;
}
}
} else {
portoption "WRITE_MODE" "READ_FIRST" {
rdwr old;
wrtrans all old;
}
}
optional_rw;
}
}
ifdef HAS_SIZE_36 {
ram block $__ANALOGDEVICES_BLOCKRAM_SDP_ {
byte 9;
option "MODE" "HALF" {
abits 14;
widths 1 2 4 9 18 36 per_port;
cost 129;
}
option "MODE" "FULL" {
abits 15;
widths 1 2 4 9 18 36 72 per_port;
cost 257;
}
init any;
port sw "W" {
ifndef HAS_MIXWIDTH_SDP {
option "MODE" "HALF" width 36;
option "MODE" "FULL" width 72;
}
ifdef HAS_ADDRCE {
# TODO
# addrce;
}
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
ifdef HAS_CONFLICT_BUG {
option "WRITE_MODE" "READ_FIRST" {
clock posedge "C";
}
option "WRITE_MODE" "WRITE_FIRST" {
clock posedge;
}
} else {
clock posedge;
}
clken;
option "WRITE_MODE" "READ_FIRST" {
wrtrans all old;
}
optional;
}
port sr "R" {
ifndef HAS_MIXWIDTH_SDP {
option "MODE" "HALF" width 36;
option "MODE" "FULL" width 72;
}
ifdef HAS_ADDRCE {
# TODO
# addrce;
}
# Spartan 6 and Virtex 6 have a bug where READ_FIRST is not usable with asynchronous clocks.
ifdef HAS_CONFLICT_BUG {
option "WRITE_MODE" "READ_FIRST" {
clock posedge "C";
}
option "WRITE_MODE" "WRITE_FIRST" {
clock posedge;
}
} else {
clock posedge;
}
clken;
rdsrst any gated_clken;
rdinit any;
optional;
}
}
}
# Single Port
# SP_1024x20
# Dual Single Port
# SP2_1024x09
# SP2_2048x05