mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-25 04:26:01 +00:00
parent
4adcbecec5
commit
4a942ba7b9
6 changed files with 37 additions and 2 deletions
23
tests/proc/bug_1268.v
Normal file
23
tests/proc/bug_1268.v
Normal file
|
@ -0,0 +1,23 @@
|
|||
module gold (input clock, ctrl, din, output reg dout);
|
||||
always @(posedge clock) begin
|
||||
if (1'b1) begin
|
||||
if (1'b0) begin end else begin
|
||||
dout <= 0;
|
||||
end
|
||||
if (ctrl)
|
||||
dout <= din;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
module gate (input clock, ctrl, din, output reg dout);
|
||||
always @(posedge clock) begin
|
||||
if (1'b1) begin
|
||||
if (1'b0) begin end else begin
|
||||
dout <= 0;
|
||||
end
|
||||
end
|
||||
if (ctrl)
|
||||
dout <= din;
|
||||
end
|
||||
endmodule
|
Loading…
Add table
Add a link
Reference in a new issue